| Message ID | 1703742157-69840-1-git-send-email-quic_qianyu@quicinc.com |
|---|---|
| Headers | show |
| Series | phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550 | expand |
On 28/12/2023 06:42, Qiang Yu wrote: > Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware > Programming Guide. > > Can Guo (1): > phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 > > Qiang Yu (1): > phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++++++------ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + > .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ > 5 files changed, 21 insertions(+), 6 deletions(-) > - On SM8550-HDK: # lspci 0000:00:00.0 PCI bridge: Qualcomm Device 0113 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) 0001:00:00.0 PCI bridge: Qualcomm Device 0113 0001:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation E12 NVMe Controller (rev 01) # lspci -nvv 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us LnkSta: Speed 5GT/s, Width x2 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us LnkSta: Speed 8GT/s, Width x2 Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK - On SM8550-QRD: # lspci 00:00.0 PCI bridge: Qualcomm Device 0113 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) # lspci -nvv LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us LnkSta: Speed 5GT/s, Width x2 Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Thanks, Neil
On 1/24/2024 4:58 PM, neil.armstrong@linaro.org wrote: > On 28/12/2023 06:42, Qiang Yu wrote: >> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware >> Programming Guide. >> >> Can Guo (1): >> phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 >> >> Qiang Yu (1): >> phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 >> >> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 >> ++++++++++++++------ >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ >> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + >> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ >> 5 files changed, 21 insertions(+), 6 deletions(-) >> > > - On SM8550-HDK: > # lspci > 0000:00:00.0 PCI bridge: Qualcomm Device 0113 > 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) > 0001:00:00.0 PCI bridge: Qualcomm Device 0113 > 0001:01:00.0 Non-Volatile memory controller: Phison Electronics > Corporation E12 NVMe Controller (rev 01) > > > # lspci -nvv > 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) > LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit > Latency L0s <4us, L1 <8us > LnkSta: Speed 5GT/s, Width x2 > 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) > LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, Exit > Latency L0s <4us, L1 <8us > LnkSta: Speed 8GT/s, Width x2 > > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK > > - On SM8550-QRD: > # lspci > 00:00.0 PCI bridge: Qualcomm Device 0113 > 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) > > # lspci -nvv > LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit > Latency L0s <4us, L1 <8us > LnkSta: Speed 5GT/s, Width x2 > > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD > > Thanks, > Neil Hi Neil, Thanks for testing this patch. I verified on aim300, did not see speed downgrade. Let me have a try on HDK8550. Thanks, Qiang
On 25/01/2024 03:59, Qiang Yu wrote: > > On 1/24/2024 4:58 PM, neil.armstrong@linaro.org wrote: >> On 28/12/2023 06:42, Qiang Yu wrote: >>> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware >>> Programming Guide. >>> >>> Can Guo (1): >>> phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 >>> >>> Qiang Yu (1): >>> phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 >>> >>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++++++------ >>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ >>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ >>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + >>> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ >>> 5 files changed, 21 insertions(+), 6 deletions(-) >>> >> >> - On SM8550-HDK: >> # lspci >> 0000:00:00.0 PCI bridge: Qualcomm Device 0113 >> 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >> 0001:00:00.0 PCI bridge: Qualcomm Device 0113 >> 0001:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation E12 NVMe Controller (rev 01) >> >> >> # lspci -nvv >> 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >> LnkSta: Speed 5GT/s, Width x2 >> 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >> LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >> LnkSta: Speed 8GT/s, Width x2 >> >> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK >> >> - On SM8550-QRD: >> # lspci >> 00:00.0 PCI bridge: Qualcomm Device 0113 >> 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >> >> # lspci -nvv >> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >> LnkSta: Speed 5GT/s, Width x2 >> >> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD >> >> Thanks, >> Neil > > Hi Neil, > > Thanks for testing this patch. I verified on aim300, did not see speed downgrade. Let me have a try on HDK8550. I haven't seen speed downgrade either on the HDK8550 Neil > > Thanks, > Qiang >
On 1/25/24 08:53, neil.armstrong@linaro.org wrote: > On 25/01/2024 03:59, Qiang Yu wrote: >> >> On 1/24/2024 4:58 PM, neil.armstrong@linaro.org wrote: >>> On 28/12/2023 06:42, Qiang Yu wrote: >>>> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware >>>> Programming Guide. >>>> >>>> Can Guo (1): >>>> phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 >>>> >>>> Qiang Yu (1): >>>> phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 >>>> >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++++++------ >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ >>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + >>>> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ >>>> 5 files changed, 21 insertions(+), 6 deletions(-) >>>> >>> >>> - On SM8550-HDK: >>> # lspci >>> 0000:00:00.0 PCI bridge: Qualcomm Device 0113 >>> 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >>> 0001:00:00.0 PCI bridge: Qualcomm Device 0113 >>> 0001:01:00.0 Non-Volatile memory controller: Phison Electronics Corporation E12 NVMe Controller (rev 01) >>> >>> >>> # lspci -nvv >>> 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >>> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >>> LnkSta: Speed 5GT/s, Width x2 >>> 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >>> LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >>> LnkSta: Speed 8GT/s, Width x2 >>> >>> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK >>> >>> - On SM8550-QRD: >>> # lspci >>> 00:00.0 PCI bridge: Qualcomm Device 0113 >>> 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >>> >>> # lspci -nvv >>> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <4us, L1 <8us >>> LnkSta: Speed 5GT/s, Width x2 >>> >>> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD >>> >>> Thanks, >>> Neil >> >> Hi Neil, >> >> Thanks for testing this patch. I verified on aim300, did not see speed downgrade. Let me have a try on HDK8550. > > I haven't seen speed downgrade either on the HDK8550 I'm guessing the 5 GT/s link goes to the Wi-Fi chip, which may be negotiating a lower PCIe gen in order to save power. Konrad
On 1/25/2024 5:51 PM, Konrad Dybcio wrote: > > > On 1/25/24 08:53, neil.armstrong@linaro.org wrote: >> On 25/01/2024 03:59, Qiang Yu wrote: >>> >>> On 1/24/2024 4:58 PM, neil.armstrong@linaro.org wrote: >>>> On 28/12/2023 06:42, Qiang Yu wrote: >>>>> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware >>>>> Programming Guide. >>>>> >>>>> Can Guo (1): >>>>> phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550 >>>>> >>>>> Qiang Yu (1): >>>>> phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550 >>>>> >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 >>>>> ++++++++++++++------ >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++ >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++ >>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 + >>>>> .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++ >>>>> 5 files changed, 21 insertions(+), 6 deletions(-) >>>>> >>>> >>>> - On SM8550-HDK: >>>> # lspci >>>> 0000:00:00.0 PCI bridge: Qualcomm Device 0113 >>>> 0000:01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >>>> 0001:00:00.0 PCI bridge: Qualcomm Device 0113 >>>> 0001:01:00.0 Non-Volatile memory controller: Phison Electronics >>>> Corporation E12 NVMe Controller (rev 01) >>>> >>>> >>>> # lspci -nvv >>>> 0000:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >>>> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, >>>> Exit Latency L0s <4us, L1 <8us >>>> LnkSta: Speed 5GT/s, Width x2 >>>> 0001:00:00.0 0604: 17cb:0113 (prog-if 00 [Normal decode]) >>>> LnkCap: Port #0, Speed 16GT/s, Width x2, ASPM L0s L1, >>>> Exit Latency L0s <4us, L1 <8us >>>> LnkSta: Speed 8GT/s, Width x2 >>>> >>>> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK >>>> >>>> - On SM8550-QRD: >>>> # lspci >>>> 00:00.0 PCI bridge: Qualcomm Device 0113 >>>> 01:00.0 Network controller: Qualcomm Device 1107 (rev 01) >>>> >>>> # lspci -nvv >>>> LnkCap: Port #0, Speed 8GT/s, Width x2, ASPM L0s L1, >>>> Exit Latency L0s <4us, L1 <8us >>>> LnkSta: Speed 5GT/s, Width x2 >>>> >>>> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD >>>> >>>> Thanks, >>>> Neil >>> >>> Hi Neil, >>> >>> Thanks for testing this patch. I verified on aim300, did not see >>> speed downgrade. Let me have a try on HDK8550. >> >> I haven't seen speed downgrade either on the HDK8550 > > I'm guessing the 5 GT/s link goes to the Wi-Fi chip, which may > be negotiating a lower PCIe gen in order to save power. > > Konrad Hi Konrad,Neil. OK, I see. I misunderstood. Thanks.