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[v3,0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P

Message ID 1700051821-1087-1-git-send-email-quic_msarkar@quicinc.com
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Series arm64: qcom: sa8775p: add cache coherency support for SA8775P | expand

Message

Mrinmay Sarkar Nov. 15, 2023, 12:36 p.m. UTC 
In a multiprocessor system cache snooping maintains the consistency
of caches. Snooping logic is disabled from HW on this platform.
Cache coherency doesn’t work without enabling this logic.

This series is to enable cache snooping logic in both RC and EP
driver and add the "dma-coherent" property in dtsi to support
cache coherency in 8775 platform.

To verify this series we required [1]

[1] https://lore.kernel.org/all/1699669982-7691-1-git-send-email-quic_msarkar@quicinc.com/

v2 -> v3:
- update commit message(8755 -> 8775).

v1 -> v2:
- update cover letter with explanation.
- define each of these bits and ORing at usage time rather than
  directly writing value in register.

Mrinmay Sarkar (3):
  PCI: qcom: Enable cache coherency for SA8775P RC
  PCI: qcom-ep: Enable cache coherency for SA8775P EP
  arm64: dts: qcom: sa8775p: Mark PCIe controller as cache coherent

 arch/arm64/boot/dts/qcom/sa8775p.dtsi     |  1 +
 drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 ++++++++++
 drivers/pci/controller/dwc/pcie-qcom.c    | 13 +++++++++++++
 3 files changed, 24 insertions(+)

Comments

Manivannan Sadhasivam Nov. 17, 2023, 8:10 a.m. UTC | #1 
On Wed, Nov 15, 2023 at 03:21:26PM +0200, Dmitry Baryshkov wrote:
> On Wed, 15 Nov 2023 at 15:18, Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> >
> > On Wed, 15 Nov 2023 at 14:37, Mrinmay Sarkar <quic_msarkar@quicinc.com> wrote:
> > >
> > > This change will enable cache snooping logic to support
> > > cache coherency for 8775 RC platform.
> > >
> > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> > > ---
> > >  drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
> > >  1 file changed, 13 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 6902e97..b82ccd1 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -51,6 +51,7 @@
> > >  #define PARF_SID_OFFSET                                0x234
> > >  #define PARF_BDF_TRANSLATE_CFG                 0x24c
> > >  #define PARF_SLV_ADDR_SPACE_SIZE               0x358
> > > +#define PCIE_PARF_NO_SNOOP_OVERIDE             0x3d4
> > >  #define PARF_DEVICE_TYPE                       0x1000
> > >  #define PARF_BDF_TO_SID_TABLE_N                        0x2000
> > >
> > > @@ -117,6 +118,10 @@
> > >  /* PARF_LTSSM register fields */
> > >  #define LTSSM_EN                               BIT(8)
> > >
> > > +/* PARF_NO_SNOOP_OVERIDE register fields */
> > > +#define WR_NO_SNOOP_OVERIDE_EN                 BIT(1)
> > > +#define RD_NO_SNOOP_OVERIDE_EN                 BIT(3)
> > > +
> > >  /* PARF_DEVICE_TYPE register fields */
> > >  #define DEVICE_TYPE_RC                         0x4
> > >
> > > @@ -961,6 +966,14 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
> > >
> > >  static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
> > >  {
> > > +       struct dw_pcie *pci = pcie->pci;
> > > +       struct device *dev = pci->dev;
> > > +
> > > +       /* Enable cache snooping for SA8775P */
> > > +       if (of_device_is_compatible(dev->of_node, "qcom,pcie-sa8775p"))
> >
> > Quoting my feedback from v1:
> >
> > Obviously: please populate a flag in the data structures instead of
> > doing of_device_is_compatible(). Same applies to the patch 2.
> 
> Mani, I saw your response for the v1, but I forgot to respond. In my
> opinion, it's better to have the flag now, even if it is just for a
> single platform. It allows us to follow the logic of the driver and
> saves few string ops.
> 

Ok, I do not have a strong opinion on this.

- Mani

> >
> >
> > > +               writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
> > > +                               pcie->parf + PCIE_PARF_NO_SNOOP_OVERIDE);
> > > +
> > >         qcom_pcie_clear_hpc(pcie->pci);
> > >
> > >         return 0;
> > > --
> > > 2.7.4
> > >
> >
> >
> > --
> > With best wishes
> > Dmitry
> 
> 
> 
> -- 
> With best wishes
> Dmitry
Manivannan Sadhasivam Nov. 17, 2023, 8:19 a.m. UTC | #2 
On Wed, Nov 15, 2023 at 06:06:59PM +0530, Mrinmay Sarkar wrote:
> This change will enable cache snooping logic to support
> cache coherency for 8775 RC platform.
> 

Please add information on why the cache snoop logic is enabled only on this
platform. You have added info in the cover letter, but that's not going to be
part of the git history.

- Mani

> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 6902e97..b82ccd1 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -51,6 +51,7 @@
>  #define PARF_SID_OFFSET				0x234
>  #define PARF_BDF_TRANSLATE_CFG			0x24c
>  #define PARF_SLV_ADDR_SPACE_SIZE		0x358
> +#define PCIE_PARF_NO_SNOOP_OVERIDE		0x3d4
>  #define PARF_DEVICE_TYPE			0x1000
>  #define PARF_BDF_TO_SID_TABLE_N			0x2000
>  
> @@ -117,6 +118,10 @@
>  /* PARF_LTSSM register fields */
>  #define LTSSM_EN				BIT(8)
>  
> +/* PARF_NO_SNOOP_OVERIDE register fields */
> +#define WR_NO_SNOOP_OVERIDE_EN			BIT(1)
> +#define RD_NO_SNOOP_OVERIDE_EN			BIT(3)
> +
>  /* PARF_DEVICE_TYPE register fields */
>  #define DEVICE_TYPE_RC				0x4
>  
> @@ -961,6 +966,14 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
>  
>  static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
>  {
> +	struct dw_pcie *pci = pcie->pci;
> +	struct device *dev = pci->dev;
> +
> +	/* Enable cache snooping for SA8775P */
> +	if (of_device_is_compatible(dev->of_node, "qcom,pcie-sa8775p"))
> +		writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
> +				pcie->parf + PCIE_PARF_NO_SNOOP_OVERIDE);
> +
>  	qcom_pcie_clear_hpc(pcie->pci);
>  
>  	return 0;
> -- 
> 2.7.4
>
Manivannan Sadhasivam Nov. 17, 2023, 9:06 a.m. UTC | #3 
On Wed, Nov 15, 2023 at 06:07:01PM +0530, Mrinmay Sarkar wrote:
> The PCIe controller on SA8775P supports cache coherency, hence add the

"PCIe RC controller" both in subject and description.

> "dma-coherent" property to mark it as such.
> 
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>

With that,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 7eab458..ab01efe 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3620,6 +3620,7 @@
>  				<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
>  		interconnect-names = "pcie-mem", "cpu-pcie";
>  
> +		dma-coherent;
>  		iommus = <&pcie_smmu 0x0000 0x7f>;
>  		resets = <&gcc GCC_PCIE_0_BCR>;
>  		reset-names = "core";
> -- 
> 2.7.4
>