| Message ID | 1687246361-23607-1-git-send-email-quic_taozha@quicinc.com |
|---|---|
| Headers | show |
| Series | Add support to configure TPDM DSB subunit | expand |
On Tue, 20 Jun 2023 15:32:40 +0800, Tao Zhang wrote: > Add property "qcom,dsb-msrs-num" to support DSB(Discrete Single > Bit) MSR(mux select register) for TPDM. It specifies the number > of MSR registers supported by the DSB TDPM. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > --- > Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Wed, Jun 28, 2023 at 11:11:29AM +0800, Tao Zhang wrote: > > On 6/20/2023 4:49 PM, Greg Kroah-Hartman wrote: > > On Tue, Jun 20, 2023 at 04:31:59PM +0800, Tao Zhang wrote: > > > On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: > > > > On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: > > > > > Add the nodes to set value for DSB edge control and DSB edge > > > > > control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR > > > > > resgisters to configure edge control. DSB edge detection control > > > > > 00: Rising edge detection > > > > > 01: Falling edge detection > > > > > 10: Rising and falling edge detection (toggle detection) > > > > > And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to > > > > > configure mask. Eight 32 bit registers providing DSB interface > > > > > edge detection mask control. > > > > > > > > > > Signed-off-by: Tao Zhang<quic_taozha@quicinc.com> > > > > > --- > > > > > .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ > > > > > drivers/hwtracing/coresight/coresight-tpdm.c | 143 ++++++++++++++++++++- > > > > > drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ > > > > > 3 files changed, 196 insertions(+), 1 deletion(-) > > > > > > > > > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > > > > > index 2a82cd0..34189e4a 100644 > > > > > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > > > > > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > > > > > @@ -60,3 +60,35 @@ Description: > > > > > Bit[3] : Set to 0 for low performance mode. > > > > > Set to 1 for high performance mode. > > > > > Bit[4:8] : Select byte lane for high performance mode. > > > > > + > > > > > +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl > > > > > +Date: March 2023 > > > > > +KernelVersion 6.5 > > > > > +Contact: Jinlong Mao (QUIC)<quic_jinlmao@quicinc.com>, Tao Zhang (QUIC)<quic_taozha@quicinc.com> > > > > > +Description: > > > > > + Read/Write a set of the edge control registers of the DSB > > > > > + in TPDM. > > > > > + > > > > > + Expected format is the following: > > > > > + <integer1> <integer2> <integer3> > > > > sysfs is "one value", not 3. Please never have to parse a sysfs file. > > > Do you mean sysfs file can only accept "one value"? > > Yes. > > Hi Greg, > > > I‘d like to clarify the usage of this sysfs file again. > > In the current design, three integers will be written to "dsb_edge_ctrl" to > configure DSB edge detection. > > Integer #1: The start number of edge detection which needs to be configured. > > Integer #2: The end number of edge detection which needs to be configured. > > Integer #3: The type of the edge detection needs to be configured. All of this is wrong. Again, sysfs is "one value per file" > Below is an example. > > echo 0x3 0x25 0x1 > dsb_edge_ctrl > > It will configure edge detection #3 to #37 as "falling edge detection". > > Since these three integers are interrelated and written to achieve the same > function, can we use these three integers as "one tuple" here? Nope! sorry, greg k-h
On 6/20/2023 9:41 PM, Suzuki K Poulose wrote: > On 20/06/2023 09:31, Tao Zhang wrote: >> >> On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: >>> On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: >>>> Add the nodes to set value for DSB edge control and DSB edge >>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR >>>> resgisters to configure edge control. DSB edge detection control >>>> 00: Rising edge detection >>>> 01: Falling edge detection >>>> 10: Rising and falling edge detection (toggle detection) >>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to >>>> configure mask. Eight 32 bit registers providing DSB interface >>>> edge detection mask control. >>>> >>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >>>> --- >>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ >>>> drivers/hwtracing/coresight/coresight-tpdm.c | 143 >>>> ++++++++++++++++++++- >>>> drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ >>>> 3 files changed, 196 insertions(+), 1 deletion(-) >>>> >>>> diff --git >>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> index 2a82cd0..34189e4a 100644 >>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>> @@ -60,3 +60,35 @@ Description: >>>> Bit[3] : Set to 0 for low performance mode. >>>> Set to 1 for high performance mode. >>>> Bit[4:8] : Select byte lane for high performance mode. >>>> + >>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl >>>> +Date: March 2023 >>>> +KernelVersion 6.5 >>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao >>>> Zhang (QUIC) <quic_taozha@quicinc.com> >>>> +Description: >>>> + Read/Write a set of the edge control registers of the DSB >>>> + in TPDM. >>>> + >>>> + Expected format is the following: >>>> + <integer1> <integer2> <integer3> >>> sysfs is "one value", not 3. Please never have to parse a sysfs file. >> >> Do you mean sysfs file can only accept "one value"? >> >> I see that more than one value are written to the sysfs file >> "trigout_attach". >> >>> >>>> +static ssize_t dsb_edge_ctrl_show(struct device *dev, >>>> + struct device_attribute *attr, >>>> + char *buf) >>>> +{ >>>> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>> + ssize_t size = 0; >>>> + unsigned long bytes; >>>> + int i; >>>> + >>>> + spin_lock(&drvdata->spinlock); >>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { >>>> + bytes = sysfs_emit_at(buf, size, >>>> + "Index:0x%x Val:0x%x\n", i, >>> Again, no, one value, no "string" needed to parse anything. >> >> I also see other sysfs files can be read more than one value in other >> drivers. >> >> Is this "one value" limitation the usage rule of Linux sysfs system? >> >> Or am I misunderstanding what you mean? > > Please fix the other sysfs tunables in the following patches. List a new solution for the similar cases below, please see if this design is reasonable? 1. Two SysFS files("dsb_edge_ctrl_idx" and "dsb_edge_ctrl_val") will be created in this case. 2. First write to the node "dsb_edge_ctrl_idx" to set the index number of the edge detection. 3. Then write to the node "dsb_edge_ctrl_val" to set the value of the edge detection. For example, if we need need to set "Falling edge detection" to the edge detection #220-#222, we can issue the following commands. echo 0xdc > tpdm1/dsb_edge_ctrl_idx echo 0x1 > tpdm1/dsb_edge_ctrl_val echo 0xdd > tpdm1/dsb_edge_ctrl_idx echo 0x1 > tpdm1/dsb_edge_ctrl_val echo 0xde > tpdm1/dsb_edge_ctrl_idx echo 0x1 > tpdm1/dsb_edge_ctrl_val If this design is acceptable, we will rewrite other similar nodes based on this solution. Let me know if you have any concerns or good suggestions for this solution. Best, Tao > > Kind regards > Suzuki > >
HI Tao, On Wed, 12 Jul 2023 at 14:53, Tao Zhang <quic_taozha@quicinc.com> wrote: > > > On 6/20/2023 9:41 PM, Suzuki K Poulose wrote: > > On 20/06/2023 09:31, Tao Zhang wrote: > >> > >> On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: > >>> On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: > >>>> Add the nodes to set value for DSB edge control and DSB edge > >>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR > >>>> resgisters to configure edge control. DSB edge detection control > >>>> 00: Rising edge detection > >>>> 01: Falling edge detection > >>>> 10: Rising and falling edge detection (toggle detection) > >>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to > >>>> configure mask. Eight 32 bit registers providing DSB interface > >>>> edge detection mask control. > >>>> > >>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > >>>> --- > >>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ > >>>> drivers/hwtracing/coresight/coresight-tpdm.c | 143 > >>>> ++++++++++++++++++++- > >>>> drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ > >>>> 3 files changed, 196 insertions(+), 1 deletion(-) > >>>> > >>>> diff --git > >>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > >>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > >>>> index 2a82cd0..34189e4a 100644 > >>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > >>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm > >>>> @@ -60,3 +60,35 @@ Description: > >>>> Bit[3] : Set to 0 for low performance mode. > >>>> Set to 1 for high performance mode. > >>>> Bit[4:8] : Select byte lane for high performance mode. > >>>> + > >>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl > >>>> +Date: March 2023 > >>>> +KernelVersion 6.5 > >>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao > >>>> Zhang (QUIC) <quic_taozha@quicinc.com> > >>>> +Description: > >>>> + Read/Write a set of the edge control registers of the DSB > >>>> + in TPDM. > >>>> + > >>>> + Expected format is the following: > >>>> + <integer1> <integer2> <integer3> > >>> sysfs is "one value", not 3. Please never have to parse a sysfs file. > >> > >> Do you mean sysfs file can only accept "one value"? > >> > >> I see that more than one value are written to the sysfs file > >> "trigout_attach". > >> > >>> > >>>> +static ssize_t dsb_edge_ctrl_show(struct device *dev, > >>>> + struct device_attribute *attr, > >>>> + char *buf) > >>>> +{ > >>>> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); > >>>> + ssize_t size = 0; > >>>> + unsigned long bytes; > >>>> + int i; > >>>> + > >>>> + spin_lock(&drvdata->spinlock); > >>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { > >>>> + bytes = sysfs_emit_at(buf, size, > >>>> + "Index:0x%x Val:0x%x\n", i, > >>> Again, no, one value, no "string" needed to parse anything. > >> > >> I also see other sysfs files can be read more than one value in other > >> drivers. > >> > >> Is this "one value" limitation the usage rule of Linux sysfs system? > >> > >> Or am I misunderstanding what you mean? > > > > Please fix the other sysfs tunables in the following patches. > > List a new solution for the similar cases below, please see if this > design is reasonable? > > 1. Two SysFS files("dsb_edge_ctrl_idx" and "dsb_edge_ctrl_val") will be > created in this case. > > 2. First write to the node "dsb_edge_ctrl_idx" to set the index number > of the edge detection. > > 3. Then write to the node "dsb_edge_ctrl_val" to set the value of the > edge detection. > > For example, if we need need to set "Falling edge detection" to the edge > detection #220-#222, we can issue the following commands. > > echo 0xdc > tpdm1/dsb_edge_ctrl_idx > > echo 0x1 > tpdm1/dsb_edge_ctrl_val > > echo 0xdd > tpdm1/dsb_edge_ctrl_idx > > echo 0x1 > tpdm1/dsb_edge_ctrl_val > > echo 0xde > tpdm1/dsb_edge_ctrl_idx > > echo 0x1 > tpdm1/dsb_edge_ctrl_val > > If this design is acceptable, we will rewrite other similar nodes based > on this solution. > This index / value model is used in the coresight drivers so should be OK - eg etm4 has cntr_idx / cntrldvr / cntr_val / cntr_ctrl, where index selects the counter, and the other val registers are applied to that counter. Mike > Let me know if you have any concerns or good suggestions for this solution. > > > Best, > > Tao > > > > > Kind regards > > Suzuki > > > >
On 13/07/2023 09:54, Mike Leach wrote: > HI Tao, > > On Wed, 12 Jul 2023 at 14:53, Tao Zhang <quic_taozha@quicinc.com> wrote: >> >> >> On 6/20/2023 9:41 PM, Suzuki K Poulose wrote: >>> On 20/06/2023 09:31, Tao Zhang wrote: >>>> >>>> On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: >>>>> On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: >>>>>> Add the nodes to set value for DSB edge control and DSB edge >>>>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR >>>>>> resgisters to configure edge control. DSB edge detection control >>>>>> 00: Rising edge detection >>>>>> 01: Falling edge detection >>>>>> 10: Rising and falling edge detection (toggle detection) >>>>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to >>>>>> configure mask. Eight 32 bit registers providing DSB interface >>>>>> edge detection mask control. >>>>>> >>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >>>>>> --- >>>>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ >>>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 143 >>>>>> ++++++++++++++++++++- >>>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ >>>>>> 3 files changed, 196 insertions(+), 1 deletion(-) >>>>>> >>>>>> diff --git >>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>> index 2a82cd0..34189e4a 100644 >>>>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>> @@ -60,3 +60,35 @@ Description: >>>>>> Bit[3] : Set to 0 for low performance mode. >>>>>> Set to 1 for high performance mode. >>>>>> Bit[4:8] : Select byte lane for high performance mode. >>>>>> + >>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl >>>>>> +Date: March 2023 >>>>>> +KernelVersion 6.5 >>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao >>>>>> Zhang (QUIC) <quic_taozha@quicinc.com> >>>>>> +Description: >>>>>> + Read/Write a set of the edge control registers of the DSB >>>>>> + in TPDM. >>>>>> + >>>>>> + Expected format is the following: >>>>>> + <integer1> <integer2> <integer3> >>>>> sysfs is "one value", not 3. Please never have to parse a sysfs file. >>>> >>>> Do you mean sysfs file can only accept "one value"? >>>> >>>> I see that more than one value are written to the sysfs file >>>> "trigout_attach". >>>> >>>>> >>>>>> +static ssize_t dsb_edge_ctrl_show(struct device *dev, >>>>>> + struct device_attribute *attr, >>>>>> + char *buf) >>>>>> +{ >>>>>> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>>>> + ssize_t size = 0; >>>>>> + unsigned long bytes; >>>>>> + int i; >>>>>> + >>>>>> + spin_lock(&drvdata->spinlock); >>>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { >>>>>> + bytes = sysfs_emit_at(buf, size, >>>>>> + "Index:0x%x Val:0x%x\n", i, >>>>> Again, no, one value, no "string" needed to parse anything. >>>> >>>> I also see other sysfs files can be read more than one value in other >>>> drivers. >>>> >>>> Is this "one value" limitation the usage rule of Linux sysfs system? >>>> >>>> Or am I misunderstanding what you mean? >>> >>> Please fix the other sysfs tunables in the following patches. >> >> List a new solution for the similar cases below, please see if this >> design is reasonable? >> >> 1. Two SysFS files("dsb_edge_ctrl_idx" and "dsb_edge_ctrl_val") will be >> created in this case. >> >> 2. First write to the node "dsb_edge_ctrl_idx" to set the index number >> of the edge detection. >> >> 3. Then write to the node "dsb_edge_ctrl_val" to set the value of the >> edge detection. >> >> For example, if we need need to set "Falling edge detection" to the edge >> detection #220-#222, we can issue the following commands. >> >> echo 0xdc > tpdm1/dsb_edge_ctrl_idx >> >> echo 0x1 > tpdm1/dsb_edge_ctrl_val >> >> echo 0xdd > tpdm1/dsb_edge_ctrl_idx >> >> echo 0x1 > tpdm1/dsb_edge_ctrl_val >> >> echo 0xde > tpdm1/dsb_edge_ctrl_idx >> >> echo 0x1 > tpdm1/dsb_edge_ctrl_val >> >> If this design is acceptable, we will rewrite other similar nodes based >> on this solution. >> > > This index / value model is used in the coresight drivers so should be > OK - eg etm4 has cntr_idx / cntrldvr / cntr_val / cntr_ctrl, where > index selects the counter, and the other val registers are applied to > that counter. True. That model is useful when there are variable number of "counters". I guess it doesn't hurt to have a 64bit (or even 32bit) file for each EDCR. e.g, edcr0...edcr15 Given there are only 16 of them, it is fine to keep a file for each. This may be grouped under "mgmt" similar to what we have for other components. That way, it can be easily hidden by checking for the presence of DSB. Suzuki
On 7/13/2023 5:34 PM, Suzuki K Poulose wrote: > On 13/07/2023 09:54, Mike Leach wrote: >> HI Tao, >> >> On Wed, 12 Jul 2023 at 14:53, Tao Zhang <quic_taozha@quicinc.com> wrote: >>> >>> >>> On 6/20/2023 9:41 PM, Suzuki K Poulose wrote: >>>> On 20/06/2023 09:31, Tao Zhang wrote: >>>>> >>>>> On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: >>>>>> On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: >>>>>>> Add the nodes to set value for DSB edge control and DSB edge >>>>>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR >>>>>>> resgisters to configure edge control. DSB edge detection control >>>>>>> 00: Rising edge detection >>>>>>> 01: Falling edge detection >>>>>>> 10: Rising and falling edge detection (toggle detection) >>>>>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to >>>>>>> configure mask. Eight 32 bit registers providing DSB interface >>>>>>> edge detection mask control. >>>>>>> >>>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >>>>>>> --- >>>>>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ >>>>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 143 >>>>>>> ++++++++++++++++++++- >>>>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ >>>>>>> 3 files changed, 196 insertions(+), 1 deletion(-) >>>>>>> >>>>>>> diff --git >>>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>> index 2a82cd0..34189e4a 100644 >>>>>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>> @@ -60,3 +60,35 @@ Description: >>>>>>> Bit[3] : Set to 0 for low performance mode. >>>>>>> Set to 1 for high performance mode. >>>>>>> Bit[4:8] : Select byte lane for high performance mode. >>>>>>> + >>>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl >>>>>>> +Date: March 2023 >>>>>>> +KernelVersion 6.5 >>>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao >>>>>>> Zhang (QUIC) <quic_taozha@quicinc.com> >>>>>>> +Description: >>>>>>> + Read/Write a set of the edge control registers of the DSB >>>>>>> + in TPDM. >>>>>>> + >>>>>>> + Expected format is the following: >>>>>>> + <integer1> <integer2> <integer3> >>>>>> sysfs is "one value", not 3. Please never have to parse a sysfs >>>>>> file. >>>>> >>>>> Do you mean sysfs file can only accept "one value"? >>>>> >>>>> I see that more than one value are written to the sysfs file >>>>> "trigout_attach". >>>>> >>>>>> >>>>>>> +static ssize_t dsb_edge_ctrl_show(struct device *dev, >>>>>>> + struct device_attribute *attr, >>>>>>> + char *buf) >>>>>>> +{ >>>>>>> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>>>>> + ssize_t size = 0; >>>>>>> + unsigned long bytes; >>>>>>> + int i; >>>>>>> + >>>>>>> + spin_lock(&drvdata->spinlock); >>>>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { >>>>>>> + bytes = sysfs_emit_at(buf, size, >>>>>>> + "Index:0x%x Val:0x%x\n", i, >>>>>> Again, no, one value, no "string" needed to parse anything. >>>>> >>>>> I also see other sysfs files can be read more than one value in other >>>>> drivers. >>>>> >>>>> Is this "one value" limitation the usage rule of Linux sysfs system? >>>>> >>>>> Or am I misunderstanding what you mean? >>>> >>>> Please fix the other sysfs tunables in the following patches. >>> >>> List a new solution for the similar cases below, please see if this >>> design is reasonable? >>> >>> 1. Two SysFS files("dsb_edge_ctrl_idx" and "dsb_edge_ctrl_val") will be >>> created in this case. >>> >>> 2. First write to the node "dsb_edge_ctrl_idx" to set the index number >>> of the edge detection. >>> >>> 3. Then write to the node "dsb_edge_ctrl_val" to set the value of the >>> edge detection. >>> >>> For example, if we need need to set "Falling edge detection" to the >>> edge >>> detection #220-#222, we can issue the following commands. >>> >>> echo 0xdc > tpdm1/dsb_edge_ctrl_idx >>> >>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>> >>> echo 0xdd > tpdm1/dsb_edge_ctrl_idx >>> >>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>> >>> echo 0xde > tpdm1/dsb_edge_ctrl_idx >>> >>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>> >>> If this design is acceptable, we will rewrite other similar nodes based >>> on this solution. >>> >> >> This index / value model is used in the coresight drivers so should be >> OK - eg etm4 has cntr_idx / cntrldvr / cntr_val / cntr_ctrl, where >> index selects the counter, and the other val registers are applied to >> that counter. > > True. That model is useful when there are variable number of "counters". > I guess it doesn't hurt to have a 64bit (or even 32bit) file for each > EDCR. > > e.g, edcr0...edcr15 > > Given there are only 16 of them, it is fine to keep a file for each. > This may be grouped under "mgmt" similar to what we have for other > components. That way, it can be easily hidden by checking for the > presence of DSB. The number of EDCR registers is not fixed. The maximum range is [0:15]. But the address of the maximum number of the registers will be reserved first, and can be accessed safely even if the TPDM doesn't have the maximum number of EDCR registers. And we are not able to dynamically know the number of EDCR registers per DSB TPDM. Can we use our proposal in this case? Best, Tao > > Suzuki >
On 13/07/2023 17:13, Tao Zhang wrote: > > On 7/13/2023 5:34 PM, Suzuki K Poulose wrote: >> On 13/07/2023 09:54, Mike Leach wrote: >>> HI Tao, >>> >>> On Wed, 12 Jul 2023 at 14:53, Tao Zhang <quic_taozha@quicinc.com> wrote: >>>> >>>> >>>> On 6/20/2023 9:41 PM, Suzuki K Poulose wrote: >>>>> On 20/06/2023 09:31, Tao Zhang wrote: >>>>>> >>>>>> On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: >>>>>>> On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: >>>>>>>> Add the nodes to set value for DSB edge control and DSB edge >>>>>>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR >>>>>>>> resgisters to configure edge control. DSB edge detection control >>>>>>>> 00: Rising edge detection >>>>>>>> 01: Falling edge detection >>>>>>>> 10: Rising and falling edge detection (toggle detection) >>>>>>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to >>>>>>>> configure mask. Eight 32 bit registers providing DSB interface >>>>>>>> edge detection mask control. >>>>>>>> >>>>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >>>>>>>> --- >>>>>>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ >>>>>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 143 >>>>>>>> ++++++++++++++++++++- >>>>>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ >>>>>>>> 3 files changed, 196 insertions(+), 1 deletion(-) >>>>>>>> >>>>>>>> diff --git >>>>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>> index 2a82cd0..34189e4a 100644 >>>>>>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>> @@ -60,3 +60,35 @@ Description: >>>>>>>> Bit[3] : Set to 0 for low performance mode. >>>>>>>> Set to 1 for high performance mode. >>>>>>>> Bit[4:8] : Select byte lane for high performance mode. >>>>>>>> + >>>>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl >>>>>>>> +Date: March 2023 >>>>>>>> +KernelVersion 6.5 >>>>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao >>>>>>>> Zhang (QUIC) <quic_taozha@quicinc.com> >>>>>>>> +Description: >>>>>>>> + Read/Write a set of the edge control registers of the DSB >>>>>>>> + in TPDM. >>>>>>>> + >>>>>>>> + Expected format is the following: >>>>>>>> + <integer1> <integer2> <integer3> >>>>>>> sysfs is "one value", not 3. Please never have to parse a sysfs >>>>>>> file. >>>>>> >>>>>> Do you mean sysfs file can only accept "one value"? >>>>>> >>>>>> I see that more than one value are written to the sysfs file >>>>>> "trigout_attach". >>>>>> >>>>>>> >>>>>>>> +static ssize_t dsb_edge_ctrl_show(struct device *dev, >>>>>>>> + struct device_attribute *attr, >>>>>>>> + char *buf) >>>>>>>> +{ >>>>>>>> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>>>>>> + ssize_t size = 0; >>>>>>>> + unsigned long bytes; >>>>>>>> + int i; >>>>>>>> + >>>>>>>> + spin_lock(&drvdata->spinlock); >>>>>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { >>>>>>>> + bytes = sysfs_emit_at(buf, size, >>>>>>>> + "Index:0x%x Val:0x%x\n", i, >>>>>>> Again, no, one value, no "string" needed to parse anything. >>>>>> >>>>>> I also see other sysfs files can be read more than one value in other >>>>>> drivers. >>>>>> >>>>>> Is this "one value" limitation the usage rule of Linux sysfs system? >>>>>> >>>>>> Or am I misunderstanding what you mean? >>>>> >>>>> Please fix the other sysfs tunables in the following patches. >>>> >>>> List a new solution for the similar cases below, please see if this >>>> design is reasonable? >>>> >>>> 1. Two SysFS files("dsb_edge_ctrl_idx" and "dsb_edge_ctrl_val") will be >>>> created in this case. >>>> >>>> 2. First write to the node "dsb_edge_ctrl_idx" to set the index number >>>> of the edge detection. >>>> >>>> 3. Then write to the node "dsb_edge_ctrl_val" to set the value of the >>>> edge detection. >>>> >>>> For example, if we need need to set "Falling edge detection" to the >>>> edge >>>> detection #220-#222, we can issue the following commands. >>>> >>>> echo 0xdc > tpdm1/dsb_edge_ctrl_idx >>>> >>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>> >>>> echo 0xdd > tpdm1/dsb_edge_ctrl_idx >>>> >>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>> >>>> echo 0xde > tpdm1/dsb_edge_ctrl_idx >>>> >>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>> >>>> If this design is acceptable, we will rewrite other similar nodes based >>>> on this solution. >>>> >>> >>> This index / value model is used in the coresight drivers so should be >>> OK - eg etm4 has cntr_idx / cntrldvr / cntr_val / cntr_ctrl, where >>> index selects the counter, and the other val registers are applied to >>> that counter. >> >> True. That model is useful when there are variable number of "counters". >> I guess it doesn't hurt to have a 64bit (or even 32bit) file for each >> EDCR. >> >> e.g, edcr0...edcr15 >> >> Given there are only 16 of them, it is fine to keep a file for each. >> This may be grouped under "mgmt" similar to what we have for other >> components. That way, it can be easily hidden by checking for the >> presence of DSB. > > The number of EDCR registers is not fixed. The maximum range is [0:15]. > > But the address of the maximum number of the registers will be reserved > first, > > and can be accessed safely even if the TPDM doesn't have the maximum number > > of EDCR registers. > > And we are not able to dynamically know the number of EDCR registers per > DSB > > TPDM. > > Can we use our proposal in this case? Please provide a file edcrN for each of the 0 <= N < 16. That way it is easier to avoid locking the index. It doesn't matter how many EDCRs are supported, there is a maximum limit and it is always guaranteed to be write safe, if some are not implemented. Thus it is much easier from a programming perspective too. Suzuki > > > Best, > > Tao > >> >> Suzuki >>
On 7/14/2023 12:37 AM, Suzuki K Poulose wrote: > On 13/07/2023 17:13, Tao Zhang wrote: >> >> On 7/13/2023 5:34 PM, Suzuki K Poulose wrote: >>> On 13/07/2023 09:54, Mike Leach wrote: >>>> HI Tao, >>>> >>>> On Wed, 12 Jul 2023 at 14:53, Tao Zhang <quic_taozha@quicinc.com> >>>> wrote: >>>>> >>>>> >>>>> On 6/20/2023 9:41 PM, Suzuki K Poulose wrote: >>>>>> On 20/06/2023 09:31, Tao Zhang wrote: >>>>>>> >>>>>>> On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: >>>>>>>> On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: >>>>>>>>> Add the nodes to set value for DSB edge control and DSB edge >>>>>>>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR >>>>>>>>> resgisters to configure edge control. DSB edge detection control >>>>>>>>> 00: Rising edge detection >>>>>>>>> 01: Falling edge detection >>>>>>>>> 10: Rising and falling edge detection (toggle detection) >>>>>>>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR >>>>>>>>> registers to >>>>>>>>> configure mask. Eight 32 bit registers providing DSB interface >>>>>>>>> edge detection mask control. >>>>>>>>> >>>>>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >>>>>>>>> --- >>>>>>>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ >>>>>>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 143 >>>>>>>>> ++++++++++++++++++++- >>>>>>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ >>>>>>>>> 3 files changed, 196 insertions(+), 1 deletion(-) >>>>>>>>> >>>>>>>>> diff --git >>>>>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>> index 2a82cd0..34189e4a 100644 >>>>>>>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>> @@ -60,3 +60,35 @@ Description: >>>>>>>>> Bit[3] : Set to 0 for low performance mode. >>>>>>>>> Set to 1 for high performance mode. >>>>>>>>> Bit[4:8] : Select byte lane for high performance mode. >>>>>>>>> + >>>>>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl >>>>>>>>> +Date: March 2023 >>>>>>>>> +KernelVersion 6.5 >>>>>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao >>>>>>>>> Zhang (QUIC) <quic_taozha@quicinc.com> >>>>>>>>> +Description: >>>>>>>>> + Read/Write a set of the edge control registers of the >>>>>>>>> DSB >>>>>>>>> + in TPDM. >>>>>>>>> + >>>>>>>>> + Expected format is the following: >>>>>>>>> + <integer1> <integer2> <integer3> >>>>>>>> sysfs is "one value", not 3. Please never have to parse a >>>>>>>> sysfs file. >>>>>>> >>>>>>> Do you mean sysfs file can only accept "one value"? >>>>>>> >>>>>>> I see that more than one value are written to the sysfs file >>>>>>> "trigout_attach". >>>>>>> >>>>>>>> >>>>>>>>> +static ssize_t dsb_edge_ctrl_show(struct device *dev, >>>>>>>>> + struct device_attribute *attr, >>>>>>>>> + char *buf) >>>>>>>>> +{ >>>>>>>>> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>>>>>>> + ssize_t size = 0; >>>>>>>>> + unsigned long bytes; >>>>>>>>> + int i; >>>>>>>>> + >>>>>>>>> + spin_lock(&drvdata->spinlock); >>>>>>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { >>>>>>>>> + bytes = sysfs_emit_at(buf, size, >>>>>>>>> + "Index:0x%x Val:0x%x\n", i, >>>>>>>> Again, no, one value, no "string" needed to parse anything. >>>>>>> >>>>>>> I also see other sysfs files can be read more than one value in >>>>>>> other >>>>>>> drivers. >>>>>>> >>>>>>> Is this "one value" limitation the usage rule of Linux sysfs >>>>>>> system? >>>>>>> >>>>>>> Or am I misunderstanding what you mean? >>>>>> >>>>>> Please fix the other sysfs tunables in the following patches. >>>>> >>>>> List a new solution for the similar cases below, please see if this >>>>> design is reasonable? >>>>> >>>>> 1. Two SysFS files("dsb_edge_ctrl_idx" and "dsb_edge_ctrl_val") >>>>> will be >>>>> created in this case. >>>>> >>>>> 2. First write to the node "dsb_edge_ctrl_idx" to set the index >>>>> number >>>>> of the edge detection. >>>>> >>>>> 3. Then write to the node "dsb_edge_ctrl_val" to set the value of the >>>>> edge detection. >>>>> >>>>> For example, if we need need to set "Falling edge detection" to >>>>> the edge >>>>> detection #220-#222, we can issue the following commands. >>>>> >>>>> echo 0xdc > tpdm1/dsb_edge_ctrl_idx >>>>> >>>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>>> >>>>> echo 0xdd > tpdm1/dsb_edge_ctrl_idx >>>>> >>>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>>> >>>>> echo 0xde > tpdm1/dsb_edge_ctrl_idx >>>>> >>>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>>> >>>>> If this design is acceptable, we will rewrite other similar nodes >>>>> based >>>>> on this solution. >>>>> >>>> >>>> This index / value model is used in the coresight drivers so should be >>>> OK - eg etm4 has cntr_idx / cntrldvr / cntr_val / cntr_ctrl, where >>>> index selects the counter, and the other val registers are applied to >>>> that counter. >>> >>> True. That model is useful when there are variable number of >>> "counters". >>> I guess it doesn't hurt to have a 64bit (or even 32bit) file for each >>> EDCR. >>> >>> e.g, edcr0...edcr15 >>> >>> Given there are only 16 of them, it is fine to keep a file for each. >>> This may be grouped under "mgmt" similar to what we have for other >>> components. That way, it can be easily hidden by checking for the >>> presence of DSB. >> >> The number of EDCR registers is not fixed. The maximum range is [0:15]. >> >> But the address of the maximum number of the registers will be >> reserved first, >> >> and can be accessed safely even if the TPDM doesn't have the maximum >> number >> >> of EDCR registers. >> >> And we are not able to dynamically know the number of EDCR registers >> per DSB >> >> TPDM. >> >> Can we use our proposal in this case? > > Please provide a file edcrN for each of the 0 <= N < 16. That way it is > easier to avoid locking the index. It doesn't matter how many EDCRs are > supported, there is a maximum limit and it is always guaranteed to be > write safe, if some are not implemented. Thus it is much easier from a > programming perspective too. Hi Suzuki, Thanks for the suggestion. I'd like to further clarify our proposal below in case I didn't express it clearly before. 1. In our design, the users don't need to know the mapping between the number of the edge detection and the control bits in EDCRN registers. They only need to focus on the edge detection they need, don't need to care about the design of the HW. 2. For example, if there are two users configure in the same test. One needs to configure edge detection #7 as "Falling edge detection". The other one needs to configure edge detection #8 as "toggle detection". They will issue the following commands to implement it. echo 0x7 > tpdm1/dsb_edge_ctrl_idx echo 0x1 > tpdm1/dsb_edge_ctrl_val echo 0x8 > tpdm1/dsb_edge_ctrl_idx echo 0x2 > tpdm1/dsb_edge_ctrl_val The value written to edcr0 will be 0x24000 in our proposal. But in the solution of "tpdm1/dsb_edge_ctrl/edcrN 0 <= N < 16". One user calculates that he needs to write 0x4000 to edcr0. echo 0x4000 > tpdm1/dsb_edge_ctrl/edcr0 The other one calculates that he needs to write 0x20000 to edcr0. echo 0x20000 > tpdm1/dsb_edge_ctrl/edcr0 The last write will overwrite the previous value in this case and 0x20000 will be written to the edcr0 finally. 3. Some DSB TPDMs may not have 16 EDCR registers. For example, TPDM2 may only have 7 EDCR registers. If we still create 16 edcr file at tpdm2/dsb_edge_ctrl, this may confuse users. Based on the above points, is it possible to re-evaluate our proposal? Best, Tao > > Suzuki > > > >> >> >> Best, >> >> Tao >> >>> >>> Suzuki >>> >
On 14/07/2023 06:50, Tao Zhang wrote: > > On 7/14/2023 12:37 AM, Suzuki K Poulose wrote: >> On 13/07/2023 17:13, Tao Zhang wrote: >>> >>> On 7/13/2023 5:34 PM, Suzuki K Poulose wrote: >>>> On 13/07/2023 09:54, Mike Leach wrote: >>>>> HI Tao, >>>>> >>>>> On Wed, 12 Jul 2023 at 14:53, Tao Zhang <quic_taozha@quicinc.com> >>>>> wrote: >>>>>> >>>>>> >>>>>> On 6/20/2023 9:41 PM, Suzuki K Poulose wrote: >>>>>>> On 20/06/2023 09:31, Tao Zhang wrote: >>>>>>>> >>>>>>>> On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: >>>>>>>>> On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: >>>>>>>>>> Add the nodes to set value for DSB edge control and DSB edge >>>>>>>>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR >>>>>>>>>> resgisters to configure edge control. DSB edge detection control >>>>>>>>>> 00: Rising edge detection >>>>>>>>>> 01: Falling edge detection >>>>>>>>>> 10: Rising and falling edge detection (toggle detection) >>>>>>>>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR >>>>>>>>>> registers to >>>>>>>>>> configure mask. Eight 32 bit registers providing DSB interface >>>>>>>>>> edge detection mask control. >>>>>>>>>> >>>>>>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >>>>>>>>>> --- >>>>>>>>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ >>>>>>>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 143 >>>>>>>>>> ++++++++++++++++++++- >>>>>>>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ >>>>>>>>>> 3 files changed, 196 insertions(+), 1 deletion(-) >>>>>>>>>> >>>>>>>>>> diff --git >>>>>>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>>> index 2a82cd0..34189e4a 100644 >>>>>>>>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>>> @@ -60,3 +60,35 @@ Description: >>>>>>>>>> Bit[3] : Set to 0 for low performance mode. >>>>>>>>>> Set to 1 for high performance mode. >>>>>>>>>> Bit[4:8] : Select byte lane for high performance mode. >>>>>>>>>> + >>>>>>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl >>>>>>>>>> +Date: March 2023 >>>>>>>>>> +KernelVersion 6.5 >>>>>>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao >>>>>>>>>> Zhang (QUIC) <quic_taozha@quicinc.com> >>>>>>>>>> +Description: >>>>>>>>>> + Read/Write a set of the edge control registers of the >>>>>>>>>> DSB >>>>>>>>>> + in TPDM. >>>>>>>>>> + >>>>>>>>>> + Expected format is the following: >>>>>>>>>> + <integer1> <integer2> <integer3> >>>>>>>>> sysfs is "one value", not 3. Please never have to parse a >>>>>>>>> sysfs file. >>>>>>>> >>>>>>>> Do you mean sysfs file can only accept "one value"? >>>>>>>> >>>>>>>> I see that more than one value are written to the sysfs file >>>>>>>> "trigout_attach". >>>>>>>> >>>>>>>>> >>>>>>>>>> +static ssize_t dsb_edge_ctrl_show(struct device *dev, >>>>>>>>>> + struct device_attribute *attr, >>>>>>>>>> + char *buf) >>>>>>>>>> +{ >>>>>>>>>> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >>>>>>>>>> + ssize_t size = 0; >>>>>>>>>> + unsigned long bytes; >>>>>>>>>> + int i; >>>>>>>>>> + >>>>>>>>>> + spin_lock(&drvdata->spinlock); >>>>>>>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { >>>>>>>>>> + bytes = sysfs_emit_at(buf, size, >>>>>>>>>> + "Index:0x%x Val:0x%x\n", i, >>>>>>>>> Again, no, one value, no "string" needed to parse anything. >>>>>>>> >>>>>>>> I also see other sysfs files can be read more than one value in >>>>>>>> other >>>>>>>> drivers. >>>>>>>> >>>>>>>> Is this "one value" limitation the usage rule of Linux sysfs >>>>>>>> system? >>>>>>>> >>>>>>>> Or am I misunderstanding what you mean? >>>>>>> >>>>>>> Please fix the other sysfs tunables in the following patches. >>>>>> >>>>>> List a new solution for the similar cases below, please see if this >>>>>> design is reasonable? >>>>>> >>>>>> 1. Two SysFS files("dsb_edge_ctrl_idx" and "dsb_edge_ctrl_val") >>>>>> will be >>>>>> created in this case. >>>>>> >>>>>> 2. First write to the node "dsb_edge_ctrl_idx" to set the index >>>>>> number >>>>>> of the edge detection. >>>>>> >>>>>> 3. Then write to the node "dsb_edge_ctrl_val" to set the value of the >>>>>> edge detection. >>>>>> >>>>>> For example, if we need need to set "Falling edge detection" to >>>>>> the edge >>>>>> detection #220-#222, we can issue the following commands. >>>>>> >>>>>> echo 0xdc > tpdm1/dsb_edge_ctrl_idx >>>>>> >>>>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>>>> >>>>>> echo 0xdd > tpdm1/dsb_edge_ctrl_idx >>>>>> >>>>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>>>> >>>>>> echo 0xde > tpdm1/dsb_edge_ctrl_idx >>>>>> >>>>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>>>> >>>>>> If this design is acceptable, we will rewrite other similar nodes >>>>>> based >>>>>> on this solution. >>>>>> >>>>> >>>>> This index / value model is used in the coresight drivers so should be >>>>> OK - eg etm4 has cntr_idx / cntrldvr / cntr_val / cntr_ctrl, where >>>>> index selects the counter, and the other val registers are applied to >>>>> that counter. >>>> >>>> True. That model is useful when there are variable number of >>>> "counters". >>>> I guess it doesn't hurt to have a 64bit (or even 32bit) file for each >>>> EDCR. >>>> >>>> e.g, edcr0...edcr15 >>>> >>>> Given there are only 16 of them, it is fine to keep a file for each. >>>> This may be grouped under "mgmt" similar to what we have for other >>>> components. That way, it can be easily hidden by checking for the >>>> presence of DSB. >>> >>> The number of EDCR registers is not fixed. The maximum range is [0:15]. >>> >>> But the address of the maximum number of the registers will be >>> reserved first, >>> >>> and can be accessed safely even if the TPDM doesn't have the maximum >>> number >>> >>> of EDCR registers. >>> >>> And we are not able to dynamically know the number of EDCR registers >>> per DSB >>> >>> TPDM. >>> >>> Can we use our proposal in this case? >> >> Please provide a file edcrN for each of the 0 <= N < 16. That way it is >> easier to avoid locking the index. It doesn't matter how many EDCRs are >> supported, there is a maximum limit and it is always guaranteed to be >> write safe, if some are not implemented. Thus it is much easier from a >> programming perspective too. > > Hi Suzuki, > > > Thanks for the suggestion. > > I'd like to further clarify our proposal below in case I didn't express > it clearly before. > > 1. In our design, the users don't need to know the mapping between the > number of the edge detection > > and the control bits in EDCRN registers. They only need to focus on the > edge detection they need, don't > > need to care about the design of the HW. Agreed > > 2. For example, if there are two users configure in the same test. One > needs to configure edge detection #7 > > as "Falling edge detection". The other one needs to configure edge > detection #8 as "toggle detection". They will > > issue the following commands to implement it. > > echo 0x7 > tpdm1/dsb_edge_ctrl_idx > > echo 0x1 > tpdm1/dsb_edge_ctrl_val > > echo 0x8 > tpdm1/dsb_edge_ctrl_idx > > echo 0x2 > tpdm1/dsb_edge_ctrl_val > > The value written to edcr0 will be 0x24000 in our proposal. > > But in the solution of "tpdm1/dsb_edge_ctrl/edcrN 0 <= N < 16". > > One user calculates that he needs to write 0x4000 to edcr0. > > echo 0x4000 > tpdm1/dsb_edge_ctrl/edcr0 > > The other one calculates that he needs to write 0x20000 to edcr0. > > echo 0x20000 > tpdm1/dsb_edge_ctrl/edcr0 > > The last write will overwrite the previous value in this case and 0x20000 > > will be written to the edcr0 finally. The solution of edcrN expects the users follow a Read-Modify-Write. But given you want to control individual lines separately (which are 256 in number), I am fine with the _idx/value solution. > > 3. Some DSB TPDMs may not have 16 EDCR registers. For example, TPDM2 > > may only have 7 EDCR registers. If we still create 16 edcr file at > tpdm2/dsb_edge_ctrl, > > this may confuse users. This is not relevant. The user can't know the maximum number anyway. If the user knows TPDM2 has only 7 EDCR, then don't bother about the other files. Please go ahead with the _idx /_value Suzuki
On 7/14/2023 6:24 PM, Suzuki K Poulose wrote: > On 14/07/2023 06:50, Tao Zhang wrote: >> >> On 7/14/2023 12:37 AM, Suzuki K Poulose wrote: >>> On 13/07/2023 17:13, Tao Zhang wrote: >>>> >>>> On 7/13/2023 5:34 PM, Suzuki K Poulose wrote: >>>>> On 13/07/2023 09:54, Mike Leach wrote: >>>>>> HI Tao, >>>>>> >>>>>> On Wed, 12 Jul 2023 at 14:53, Tao Zhang <quic_taozha@quicinc.com> >>>>>> wrote: >>>>>>> >>>>>>> >>>>>>> On 6/20/2023 9:41 PM, Suzuki K Poulose wrote: >>>>>>>> On 20/06/2023 09:31, Tao Zhang wrote: >>>>>>>>> >>>>>>>>> On 6/20/2023 3:37 PM, Greg Kroah-Hartman wrote: >>>>>>>>>> On Tue, Jun 20, 2023 at 03:32:37PM +0800, Tao Zhang wrote: >>>>>>>>>>> Add the nodes to set value for DSB edge control and DSB edge >>>>>>>>>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR >>>>>>>>>>> resgisters to configure edge control. DSB edge detection >>>>>>>>>>> control >>>>>>>>>>> 00: Rising edge detection >>>>>>>>>>> 01: Falling edge detection >>>>>>>>>>> 10: Rising and falling edge detection (toggle detection) >>>>>>>>>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR >>>>>>>>>>> registers to >>>>>>>>>>> configure mask. Eight 32 bit registers providing DSB interface >>>>>>>>>>> edge detection mask control. >>>>>>>>>>> >>>>>>>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> >>>>>>>>>>> --- >>>>>>>>>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++ >>>>>>>>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 143 >>>>>>>>>>> ++++++++++++++++++++- >>>>>>>>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 22 ++++ >>>>>>>>>>> 3 files changed, 196 insertions(+), 1 deletion(-) >>>>>>>>>>> >>>>>>>>>>> diff --git >>>>>>>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>>>> index 2a82cd0..34189e4a 100644 >>>>>>>>>>> --- >>>>>>>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>>>> +++ >>>>>>>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm >>>>>>>>>>> @@ -60,3 +60,35 @@ Description: >>>>>>>>>>> Bit[3] : Set to 0 for low performance mode. >>>>>>>>>>> Set to 1 for high performance mode. >>>>>>>>>>> Bit[4:8] : Select byte lane for high performance >>>>>>>>>>> mode. >>>>>>>>>>> + >>>>>>>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl >>>>>>>>>>> +Date: March 2023 >>>>>>>>>>> +KernelVersion 6.5 >>>>>>>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao >>>>>>>>>>> Zhang (QUIC) <quic_taozha@quicinc.com> >>>>>>>>>>> +Description: >>>>>>>>>>> + Read/Write a set of the edge control registers of >>>>>>>>>>> the DSB >>>>>>>>>>> + in TPDM. >>>>>>>>>>> + >>>>>>>>>>> + Expected format is the following: >>>>>>>>>>> + <integer1> <integer2> <integer3> >>>>>>>>>> sysfs is "one value", not 3. Please never have to parse a >>>>>>>>>> sysfs file. >>>>>>>>> >>>>>>>>> Do you mean sysfs file can only accept "one value"? >>>>>>>>> >>>>>>>>> I see that more than one value are written to the sysfs file >>>>>>>>> "trigout_attach". >>>>>>>>> >>>>>>>>>> >>>>>>>>>>> +static ssize_t dsb_edge_ctrl_show(struct device *dev, >>>>>>>>>>> + struct device_attribute *attr, >>>>>>>>>>> + char *buf) >>>>>>>>>>> +{ >>>>>>>>>>> + struct tpdm_drvdata *drvdata = >>>>>>>>>>> dev_get_drvdata(dev->parent); >>>>>>>>>>> + ssize_t size = 0; >>>>>>>>>>> + unsigned long bytes; >>>>>>>>>>> + int i; >>>>>>>>>>> + >>>>>>>>>>> + spin_lock(&drvdata->spinlock); >>>>>>>>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) { >>>>>>>>>>> + bytes = sysfs_emit_at(buf, size, >>>>>>>>>>> + "Index:0x%x Val:0x%x\n", i, >>>>>>>>>> Again, no, one value, no "string" needed to parse anything. >>>>>>>>> >>>>>>>>> I also see other sysfs files can be read more than one value >>>>>>>>> in other >>>>>>>>> drivers. >>>>>>>>> >>>>>>>>> Is this "one value" limitation the usage rule of Linux sysfs >>>>>>>>> system? >>>>>>>>> >>>>>>>>> Or am I misunderstanding what you mean? >>>>>>>> >>>>>>>> Please fix the other sysfs tunables in the following patches. >>>>>>> >>>>>>> List a new solution for the similar cases below, please see if this >>>>>>> design is reasonable? >>>>>>> >>>>>>> 1. Two SysFS files("dsb_edge_ctrl_idx" and "dsb_edge_ctrl_val") >>>>>>> will be >>>>>>> created in this case. >>>>>>> >>>>>>> 2. First write to the node "dsb_edge_ctrl_idx" to set the index >>>>>>> number >>>>>>> of the edge detection. >>>>>>> >>>>>>> 3. Then write to the node "dsb_edge_ctrl_val" to set the value >>>>>>> of the >>>>>>> edge detection. >>>>>>> >>>>>>> For example, if we need need to set "Falling edge detection" to >>>>>>> the edge >>>>>>> detection #220-#222, we can issue the following commands. >>>>>>> >>>>>>> echo 0xdc > tpdm1/dsb_edge_ctrl_idx >>>>>>> >>>>>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>>>>> >>>>>>> echo 0xdd > tpdm1/dsb_edge_ctrl_idx >>>>>>> >>>>>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>>>>> >>>>>>> echo 0xde > tpdm1/dsb_edge_ctrl_idx >>>>>>> >>>>>>> echo 0x1 > tpdm1/dsb_edge_ctrl_val >>>>>>> >>>>>>> If this design is acceptable, we will rewrite other similar >>>>>>> nodes based >>>>>>> on this solution. >>>>>>> >>>>>> >>>>>> This index / value model is used in the coresight drivers so >>>>>> should be >>>>>> OK - eg etm4 has cntr_idx / cntrldvr / cntr_val / cntr_ctrl, where >>>>>> index selects the counter, and the other val registers are >>>>>> applied to >>>>>> that counter. >>>>> >>>>> True. That model is useful when there are variable number of >>>>> "counters". >>>>> I guess it doesn't hurt to have a 64bit (or even 32bit) file for each >>>>> EDCR. >>>>> >>>>> e.g, edcr0...edcr15 >>>>> >>>>> Given there are only 16 of them, it is fine to keep a file for each. >>>>> This may be grouped under "mgmt" similar to what we have for other >>>>> components. That way, it can be easily hidden by checking for the >>>>> presence of DSB. >>>> >>>> The number of EDCR registers is not fixed. The maximum range is >>>> [0:15]. >>>> >>>> But the address of the maximum number of the registers will be >>>> reserved first, >>>> >>>> and can be accessed safely even if the TPDM doesn't have the >>>> maximum number >>>> >>>> of EDCR registers. >>>> >>>> And we are not able to dynamically know the number of EDCR >>>> registers per DSB >>>> >>>> TPDM. >>>> >>>> Can we use our proposal in this case? >>> >>> Please provide a file edcrN for each of the 0 <= N < 16. That way it is >>> easier to avoid locking the index. It doesn't matter how many EDCRs are >>> supported, there is a maximum limit and it is always guaranteed to be >>> write safe, if some are not implemented. Thus it is much easier from >>> a programming perspective too. >> >> Hi Suzuki, >> >> >> Thanks for the suggestion. >> >> I'd like to further clarify our proposal below in case I didn't >> express it clearly before. >> >> 1. In our design, the users don't need to know the mapping between >> the number of the edge detection >> >> and the control bits in EDCRN registers. They only need to focus on >> the edge detection they need, don't >> >> need to care about the design of the HW. > > Agreed > >> >> 2. For example, if there are two users configure in the same test. >> One needs to configure edge detection #7 >> >> as "Falling edge detection". The other one needs to configure edge >> detection #8 as "toggle detection". They will >> >> issue the following commands to implement it. >> >> echo 0x7 > tpdm1/dsb_edge_ctrl_idx >> >> echo 0x1 > tpdm1/dsb_edge_ctrl_val >> >> echo 0x8 > tpdm1/dsb_edge_ctrl_idx >> >> echo 0x2 > tpdm1/dsb_edge_ctrl_val >> >> The value written to edcr0 will be 0x24000 in our proposal. >> >> But in the solution of "tpdm1/dsb_edge_ctrl/edcrN 0 <= N < 16". >> >> One user calculates that he needs to write 0x4000 to edcr0. >> >> echo 0x4000 > tpdm1/dsb_edge_ctrl/edcr0 >> >> The other one calculates that he needs to write 0x20000 to edcr0. >> >> echo 0x20000 > tpdm1/dsb_edge_ctrl/edcr0 >> >> The last write will overwrite the previous value in this case and >> 0x20000 >> >> will be written to the edcr0 finally. > > The solution of edcrN expects the users follow a Read-Modify-Write. > But given you want to control individual lines separately (which are 256 > in number), I am fine with the _idx/value solution. > >> >> 3. Some DSB TPDMs may not have 16 EDCR registers. For example, TPDM2 >> >> may only have 7 EDCR registers. If we still create 16 edcr file at >> tpdm2/dsb_edge_ctrl, >> >> this may confuse users. > > This is not relevant. The user can't know the maximum number anyway. > If the user knows TPDM2 has only 7 EDCR, then don't bother about the > other > files. > > Please go ahead with the _idx /_value Thanks. I will update in the next patch series. Best, Tao > > Suzuki > _______________________________________________ > CoreSight mailing list -- coresight@lists.linaro.org > To unsubscribe send an email to coresight-leave@lists.linaro.org
Introduction of TPDM DSB subunit DSB subunit is responsible for creating a dataset element, and is also optionally responsible for packing it to fit multiple elements on a single ATB transfer if possible in the configuration. The TPDM Core Datapath requests timestamps be stored by the TPDA and then delivering ATB sized data (depending on ATB width and element size, this could be smaller or larger than a dataset element) to the ATB Mast FSM. The DSB subunit must be configured prior to enablement. This series adds support for TPDM to configure the configure DSB subunit. Once this series patches are applied properly, the new tpdm nodes for should be observed at the tpdm path /sys/bus/coresight/devices/tpdm* which supports DSB subunit. e.g. /sys/devices/platform/soc@0/69d0000.tpdm/tpdm0#ls -l | grep dsb -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_edge_ctrl_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_mode -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_type -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_mask -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_patt_val -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_ts -rw-r--r-- 1 root root 4096 Jan 1 00:01 dsb_trig_type We can use the commands are similar to the below to configure the TPDMs which support DSB subunit. Enable coresight sink first. echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink echo 1 > /sys/bus/coresight/devices/tpdm0/reset echo 0x3 0x3 0x1 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl_mask echo 0x6d 0x6d 0 > /sys/bus/coresight/devices/tpdm0/dsb_edge_ctrl echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_ts echo 1 > /sys/bus/coresight/devices/tpdm0/dsb_patt_type echo 0 > /sys/bus/coresight/devices/tpdm0/dsb_trig_ts echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_patt_mask echo 0 0xFFFFFFFF > /sys/bus/coresight/devices/tpdm0/dsb_trig_patt_val This patch series depends on patch series "[PATCH v6 0/9] coresight: Fix CTI module refcount leak by making it a helper device" https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230425143542.2305069-14-james.clark@arm.com/ TPDM_DSB commit tree: https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/tpdm-dsb-v6 https://git.codelinaro.org/clo/linux-kernel/coresight/-/commits/tpdm-dsb-v6 Changes in V6: 1. Align the code to fix the styling issue. -- Suzuki K Poulose Changes in V5: 1. Correct data type for DSB element size in dt-bindings patch. 2. Refine the recursive function "tpda_set_element_size". -- Suzuki K Poulose 3. Get return value of the function "__tpda_enable" in "tpda_enable". -- Suzuki K Poulose 4. Refine the comments on "dsb_esize". -- Suzuki K Poulose 5. Split the chage that introduce the subtype "SUBTYPE_SOURCE_TPDM" to Coresight driver. -- Suzuki K Poulose 6. Inline the trigger type setting to "tpdm_enable_dsb" simply. -- Suzuki K Poulose 7. Split the change that remove the needless CS_{UN,}LOCK in the function "tpdm_datasets_setup". -- Suzuki K Poulose 8. Remove the disablement step in the reset node. -- Suzuki K Poulose 9. Update the kernel version to 6.5 in the sysfs document. -- Suzuki K Poulose 10. Remove the needless check in "tpdm_dsb_is_visible". -- Suzuki K Poulose 11. Change the macro to mask the mode of DSB TPDM. -- Suzuki K Poulose 12. Add a check to make sure "sysfs_emit_at" calling will not cause overflow. -- Suzuki K Poulose 13. Change the macro to get "edge_ctrl" value. -- Suzuki K Poulose 14. Remove the needless comments in the sysfs document. -- Suzuki K Poulose 15. Replace "TPDM_DSB_MAX_PATT" with "drvdata->dsb->msr_num" in "dsb_msr_show". -- Suzuki K Poulose 16. Update the check of MSR number in "dsb_msr_store". -- Suzuki K Poulose 17. Write data to the MSR registers in the DSB TPDM enablement function. -- Suzuki K Poulose Changes in V4: 1. Change the range of the property "qcom,dsb-element-size", and change the type to enumeration. -- Suzuki K Poulose, Krzysztof Kozlowski 2. Change dsb_esize from 32 bits to 8 bits. -- Suzuki K Poulose 3. Update the function tpda_set_element_size since James has updated the dependency series. Meanwhile, it will send out a warning if it detects more than one TPDM from the same TPDA input port. -- Suzuki K Poulose 4. Add a source_sub_type for TPDM to distinguish TPDM from the other coresight source. -- Suzuki K Poulose 5. Return error if the element size is not configured on devicetree in TPDA enablement. -- Suzuki K Poulose 6. Move memory allocation from "tpdm_init_datasets" to "tpdm_datasets_setup". Rename "tpdm_init_datasets" as "tpdm_reset_datasets". -- Suzuki K Poulose 7. Replace "coresight_disable" with "coresight_disable_source" to disable the TPDM in resetting. -- Suzuki K Poulose 8. Make sure "drvdata" is not NULL pointer before using it. -- Suzuki K Poulose 9. Change "set_dsb_cycacc_mode" to "set_dsb_test_mode" since cycle accurate mode is not supported on the current targets. It is replaced by test mode. 10. Document the value of "dsb_mode". -- Suzuki K Poulose 11. Macros are used to replace the formulas on dsb edge control nodes. -- Suzuki K Poulose 12. Document the values of "dsb_trig_patt_val" and "dsb_trig_patt_mask". -- Suzuki K Poulose 13. Combine two pattern related loops to one. And move DSB TIER register configurations to the new function "set_dsb_tier". -- Suzuki K Poulose 14. Rename the property "qcom,dsb_msr_num" to "qcom,dsb-msrs-num". -- Suzuki K Poulose, Krzysztof Kozlowski Changes in V3: 1. Move the property "qcom,dsb-element-size" to TPDM devicetree and update the TPDM yaml file for this item. -- Suzuki K Poulose 2. Add the error message when the DSB element size is not set to 32-bit or 64-bit. -- Suzuki K Poulose 3. Add more information to the comments of patch #3 -- Suzuki K Poulose 4. Combine the value updates to the TPDM_DSB_CR for TPDM. -- Suzuki K Poulose 5. Remove the function "tpdm_datasets_alloc", and fold its code to a new function "tpdm_init_datasets". It will complete the initialization of TPDM. -- Suzuki K Poulose 6. Change the method of qualifying input values. -- Suzuki K Poulose 7. Add the documentation of the new sysfs handles. -- Suzuki K Poulose 8. Provide the separate handles for the "mode bits". -- Suzuki K Poulose Changes in V2: 1. Change the name of the property "qcom,dsb-elem-size" to "qcom,dsb-element-size" -- Suzuki K Poulose 2. Update the TPDA yaml file for the item "qcom,dsb-elem-size". -- Krzysztof Kozlowski 3. Add the full name of DSB in the description of the item "qcom,dsb-elem-size". -- Rob Herring Changes in V1: 1. Change the definition of the property "qcom,dsb-elem-size" from "uint32-array" to "uint32-matrix". -- Krzysztof Kozlowski 2. Add the full name of DSB. -- Rob Herring 3. Deal with 2 entries in an iteration in TPDA driver. -- Suzuki K Poulose 4. Divide the function "tpdm_datasets_alloc" into two functions, "tpdm_datasets_setup" and "tpdm_datasets_alloc". 5. Detecte the input string with the conventional semantics automatically, and constrain the size of the input value. -- Suzuki K Poulose 6. Use the hook function "is_visible()" to hide the DSB related knobs if the data sets are missing. -- Suzuki K Poulose 7. Use the macros "FIELD_GET" and "FIELD_PREP" to set the values. -- Suzuki K Poulose 8. Update the definition of the macros in TPDM driver. 9. Update the comments of the values for the nodes which are for DSB element creation and onfigure pattern match output. -- Suzuki K Poulose 10. Use API "sysfs_emit" to "replace scnprintf". -- Suzuki K Poulose Tao Zhang (13): coresight-tpdm: Remove the unnecessary lock dt-bindings: arm: Add support for DSB element size coresight-tpdm: Introduce TPDM subtype to TPDM driver coresight-tpda: Add DSB dataset support coresight-tpdm: Initialize DSB subunit configuration coresight-tpdm: Add reset node to TPDM node coresight-tpdm: Add nodes to set trigger timestamp and type coresight-tpdm: Add node to set dsb programming mode Add nodes for dsb edge control coresight-tpdm: Add nodes to configure pattern match output coresight-tpdm: Add nodes for timestamp request dt-bindings: arm: Add support for DSB MSR register coresight-tpdm: Add nodes for dsb msr support .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 169 +++++ .../bindings/arm/qcom,coresight-tpdm.yaml | 20 + drivers/hwtracing/coresight/coresight-core.c | 1 + drivers/hwtracing/coresight/coresight-tpda.c | 96 ++- drivers/hwtracing/coresight/coresight-tpda.h | 4 + drivers/hwtracing/coresight/coresight-tpdm.c | 721 ++++++++++++++++++++- drivers/hwtracing/coresight/coresight-tpdm.h | 83 +++ include/linux/coresight.h | 1 + 8 files changed, 1077 insertions(+), 18 deletions(-)