mbox series

[v2,0/6] Add PCIe EP support for SDX65

Message ID 1678277993-18836-1-git-send-email-quic_rohiagar@quicinc.com
Headers show
Series Add PCIe EP support for SDX65 | expand

Message

Rohit Agarwal March 8, 2023, 12:19 p.m. UTC 
Hi,

Changes in v2:
 - Addressing comments from Konrad and Dmitry.
 - Rebased on top of 6.3-rc1.

This series adds the devicetree support for PCIe PHY and PCIe EP on SDX65.
The PCIe EP is enabled on SDX65 MTP board.

Thanks,
Rohit.

Rohit Agarwal (6):
  dt-bindings: mfd: qcom,tcsr: Add compatible for sdx65
  dt-bindings: PCI: qcom: Add SDX65 SoC
  ARM: dts: qcom: sdx65: Add support for PCIe PHY
  ARM: dts: qcom: sdx65: Add support for PCIe EP
  ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY
  ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

 .../devicetree/bindings/mfd/qcom,tcsr.yaml         |  1 +
 .../devicetree/bindings/pci/qcom,pcie-ep.yaml      |  2 +
 arch/arm/boot/dts/qcom-sdx65-mtp.dts               | 50 ++++++++++--
 arch/arm/boot/dts/qcom-sdx65.dtsi                  | 92 ++++++++++++++++++++++
 4 files changed, 140 insertions(+), 5 deletions(-)

Comments

Konrad Dybcio March 8, 2023, 12:35 p.m. UTC | #1 
On 8.03.2023 13:19, Rohit Agarwal wrote:
> Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
> used by the PCIe EP controller.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>  arch/arm/boot/dts/qcom-sdx65.dtsi | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 192f9f9..df9d428 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -293,6 +293,39 @@
>  			status = "disabled";
>  		};
>  
> +		pcie_phy: phy@1c06000 {
> +			compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
> +			reg = <0x01c06000 0x2000>;

> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
No child nodes, please drop this hunk.


Konrad
> +			clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
> +				 <&gcc GCC_PCIE_CFG_AHB_CLK>,
> +				 <&gcc GCC_PCIE_0_CLKREF_EN>,
> +				 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> +				 <&gcc GCC_PCIE_PIPE_CLK>;
> +			clock-names = "aux",
> +				      "cfg_ahb",
> +				      "ref",
> +				      "rchng",
> +				      "pipe";
> +
> +			resets = <&gcc GCC_PCIE_PHY_BCR>;
> +			reset-names = "phy";
> +
> +			assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> +			assigned-clock-rates = <100000000>;
> +
> +			power-domains = <&gcc PCIE_GDSC>;
> +
> +			#clock-cells = <0>;
> +			clock-output-names = "pcie_pipe_clk";
> +
> +			#phy-cells = <0>;
> +
> +			status = "disabled";
> +		};
> +
>  		tcsr_mutex: hwlock@1f40000 {
>  			compatible = "qcom,tcsr-mutex";
>  			reg = <0x01f40000 0x40000>;
Rohit Agarwal March 8, 2023, 1:10 p.m. UTC | #2 
On 3/8/2023 6:08 PM, Konrad Dybcio wrote:
>
> On 8.03.2023 13:19, Rohit Agarwal wrote:
>> Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it,
>> updating status as last property for each node.
>>
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
>>   arch/arm/boot/dts/qcom-sdx65-mtp.dts | 20 +++++++++++++++-----
>>   1 file changed, 15 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> index ed98c83..facb8e2 100644
>> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> @@ -245,13 +245,18 @@
>>   	status = "okay";
>>   };
>>   
>> -&qpic_bam {
>> +&pcie_phy {
>> +	vdda-phy-supply = <&vreg_l1b_1p2>;
>> +	vdda-pll-supply = <&vreg_l4b_0p88>;
>> +
>>   	status = "okay";
>>   };
>>   
>> -&qpic_nand {
>> +&qpic_bam {
>>   	status = "okay";
>> +};
>>   
>> +&qpic_nand {
>>   	nand@0 {
>>   		reg = <0>;
>>   
>> @@ -262,11 +267,14 @@
>>   		secure-regions = /bits/ 64 <0x500000 0x500000
>>   					    0xa00000 0xb00000>;
>>   	};
>> +
>> +	status = "okay";
> Did you compiletest this?

So Sorry, Missed some of the patches for compiletest.
Will update immediately.

Thanks,
Rohit.
>
> Konrad
>>   };
>>   
>>   &remoteproc_mpss {
>> -	status = "okay";
>>   	memory-region = <&mpss_adsp_mem>;
>> +
>> +	status = "okay";
>>   };
>>   
>>   &usb {
>> @@ -278,14 +286,16 @@
>>   };
>>   
>>   &usb_hsphy {
>> -	status = "okay";
>>   	vdda-pll-supply = <&vreg_l4b_0p88>;
>>   	vdda33-supply = <&vreg_l10b_3p08>;
>>   	vdda18-supply = <&vreg_l5b_1p8>;
>> +
>> +	status = "okay";
>>   };
>>   
>>   &usb_qmpphy {
>> -	status = "okay";
>>   	vdda-phy-supply = <&vreg_l4b_0p88>;
>>   	vdda-pll-supply = <&vreg_l1b_1p2>;
>> +
>> +	status = "okay";
>>   };