From patchwork Thu Aug 18 20:18:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 598579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23A1BC3F6B0 for ; Thu, 18 Aug 2022 20:19:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237254AbiHRUTL (ORCPT ); Thu, 18 Aug 2022 16:19:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232033AbiHRUTK (ORCPT ); Thu, 18 Aug 2022 16:19:10 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9010594120; Thu, 18 Aug 2022 13:19:09 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IGLoZr024158; Thu, 18 Aug 2022 20:18:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=u0fa4c5sD2eB6IMzsFRWJT5E5T+P+DVvpkmV/TCgS8o=; b=QJQHJmZeC54S3Ul8SdObNljBe+8ESWqiXIc5+8/R9s0qdUC/JXHNRvoRFZKhA2iRRGDW 4I9lUsECsVN1CakHYV3MqzmyD6Kghj96ABao9SeB44j5Vx/HDlkII2VH2aoiLeTbJ494 PWCSw/2IoF3fTvXy8yMWruInO5J8t/2WRdjhSoI2/1U1+nc4YF4pwNUy7kmqT+3iN9YS rgfx/IuJBo+SDeYGX3hHe51FqdwY0SJHnGWB4Oa0krC7m6+1YK/0FlCXq1HunuoyDGN9 KekYS+hDSnIHuYA1Cz2VUYF6zeqoTM3XwwIm05gFgyiEcJfyAiC8NFUdaEqA7R3Dlj+G 6A== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3j1rvb0t09-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 20:18:58 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27IKIvS3019713 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 20:18:57 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 18 Aug 2022 13:18:52 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" , Dmitry Baryshkov CC: Douglas Anderson , , Akhil P Oommen , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Rob Herring , Stephen Boyd , , , Subject: [PATCH v3 0/5] clk/qcom: Support gdsc collapse polling using 'reset' inteface Date: Fri, 19 Aug 2022 01:48:34 +0530 Message-ID: <1660853919-987-1-git-send-email-quic_akhilpo@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rUd7NoZLXLnunYI86YZikc3uStvdA_Kl X-Proofpoint-GUID: rUd7NoZLXLnunYI86YZikc3uStvdA_Kl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_14,2022-08-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 mlxlogscore=771 impostorscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208180074 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some clients like adreno gpu driver would like to ensure that its gdsc is collapsed at hardware during a gpu reset sequence. This is because it has a votable gdsc which could be ON due to a vote from another subsystem like tz, hyp etc or due to an internal hardware signal. To allow this, gpucc driver can expose an interface to the client driver using reset framework. Using this the client driver can trigger a polling within the gdsc driver. This series is rebased on top of linus's master branch. Related discussion: https://patchwork.freedesktop.org/patch/493144/ Changes in v3: - Use pointer to const for "struct qcom_reset_ops" in qcom_reset_map (Krzysztof) Changes in v2: - Return error when a particular custom reset op is not implemented. (Dmitry) Akhil P Oommen (5): dt-bindings: clk: qcom: Support gpu cx gdsc reset clk: qcom: Allow custom reset ops clk: qcom: gdsc: Add a reset op to poll gdsc collapse clk: qcom: gpucc-sc7280: Add cx collapse reset support arm64: dts: qcom: sc7280: Add Reset support for gpu arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ drivers/clk/qcom/gdsc.c | 23 +++++++++++++++++++---- drivers/clk/qcom/gdsc.h | 7 +++++++ drivers/clk/qcom/gpucc-sc7280.c | 10 ++++++++++ drivers/clk/qcom/reset.c | 27 +++++++++++++++++++++++++++ drivers/clk/qcom/reset.h | 8 ++++++++ include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ 7 files changed, 77 insertions(+), 4 deletions(-)