| Message ID | 1624564058-24095-1-git-send-email-sibis@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add Modem support on SC7280 SoCs | expand |
Hi Sibi, On Fri, Jun 25, 2021 at 01:17:34AM +0530, Sibi Sankar wrote: > Add out of reset sequence support for modem sub-system on SC7280 SoCs. > It requires access to an additional set of qaccept registers, external > power/clk control registers and halt vq6 register to put the modem back > into reset. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > --- > drivers/remoteproc/qcom_q6v5_mss.c | 245 ++++++++++++++++++++++++++++++++++++- > 1 file changed, 241 insertions(+), 4 deletions(-) > > diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c > index 5d21084004cb..4e32811e0025 100644 > --- a/drivers/remoteproc/qcom_q6v5_mss.c > +++ b/drivers/remoteproc/qcom_q6v5_mss.c > @@ -77,6 +77,14 @@ > > #define HALT_ACK_TIMEOUT_US 100000 > > +/* QACCEPT Register Offsets */ > +#define QACCEPT_ACCEPT_REG 0x0 > +#define QACCEPT_ACTIVE_REG 0x4 > +#define QACCEPT_DENY_REG 0x8 > +#define QACCEPT_REQ_REG 0xC > + > +#define QACCEPT_TIMEOUT_US 50 > + > /* QDSP6SS_RESET */ > #define Q6SS_STOP_CORE BIT(0) > #define Q6SS_CORE_ARES BIT(1) > @@ -143,6 +151,9 @@ struct rproc_hexagon_res { > bool has_alt_reset; > bool has_mba_logs; > bool has_spare_reg; > + bool has_qaccept_regs; > + bool has_ext_cntl_regs; > + bool has_vq6; > }; > > struct q6v5 { > @@ -158,8 +169,18 @@ struct q6v5 { > u32 halt_q6; > u32 halt_modem; > u32 halt_nc; > + u32 halt_vq6; > u32 conn_box; > > + u32 qaccept_mdm; > + u32 qaccept_cx; > + u32 qaccept_axi; > + > + u32 axim1_clk_off; > + u32 crypto_clk_off; > + u32 force_clk_on; > + u32 rscc_disable; > + > struct reset_control *mss_restart; > struct reset_control *pdc_reset; > > @@ -201,6 +222,9 @@ struct q6v5 { > bool has_alt_reset; > bool has_mba_logs; > bool has_spare_reg; > + bool has_qaccept_regs; > + bool has_ext_cntl_regs; > + bool has_vq6; > int mpss_perm; > int mba_perm; > const char *hexagon_mdt_image; > @@ -213,6 +237,7 @@ enum { > MSS_MSM8996, > MSS_MSM8998, > MSS_SC7180, > + MSS_SC7280, > MSS_SDM845, > }; > > @@ -473,6 +498,12 @@ static int q6v5_reset_assert(struct q6v5 *qproc) > regmap_update_bits(qproc->conn_map, qproc->conn_box, > AXI_GATING_VALID_OVERRIDE, 0); > ret = reset_control_deassert(qproc->mss_restart); > + } else if (qproc->has_ext_cntl_regs) { > + regmap_write(qproc->conn_map, qproc->rscc_disable, 0); > + reset_control_assert(qproc->pdc_reset); > + reset_control_assert(qproc->mss_restart); > + reset_control_deassert(qproc->pdc_reset); > + ret = reset_control_deassert(qproc->mss_restart); > } else { > ret = reset_control_assert(qproc->mss_restart); > } > @@ -490,7 +521,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc) > ret = reset_control_reset(qproc->mss_restart); > writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); > reset_control_deassert(qproc->pdc_reset); > - } else if (qproc->has_spare_reg) { > + } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) { > ret = reset_control_reset(qproc->mss_restart); > } else { > ret = reset_control_deassert(qproc->mss_restart); > @@ -604,7 +635,7 @@ static int q6v5proc_reset(struct q6v5 *qproc) > } > > goto pbl_wait; > - } else if (qproc->version == MSS_SC7180) { > + } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) { > val = readl(qproc->reg_base + QDSP6SS_SLEEP); > val |= Q6SS_CBCR_CLKEN; > writel(val, qproc->reg_base + QDSP6SS_SLEEP); > @@ -787,6 +818,82 @@ static int q6v5proc_reset(struct q6v5 *qproc) > return ret; > } > > +static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset) > +{ > + unsigned int val; > + int ret; > + > + if (!qproc->has_qaccept_regs) > + return 0; > + > + if (qproc->has_ext_cntl_regs) { > + regmap_write(qproc->conn_map, qproc->rscc_disable, 0); > + regmap_write(qproc->conn_map, qproc->force_clk_on, 1); > + > + ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val, > + !val, 1, Q6SS_CBCR_TIMEOUT_US); > + if (ret) { > + dev_err(qproc->dev, "failed to enable axim1 clock\n"); > + return -ETIMEDOUT; > + } > + } > + > + regmap_write(map, offset + QACCEPT_REQ_REG, 1); > + > + /* Wait for accept */ > + ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5, > + QACCEPT_TIMEOUT_US); > + if (ret) { > + dev_err(qproc->dev, "qchannel enable failed\n"); > + return -ETIMEDOUT; > + } > + > + return 0; > +} > + > +static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset) > +{ > + int ret; > + unsigned int val, retry; > + unsigned int nretry = 10; > + bool takedown_complete = false; > + > + if (!qproc->has_qaccept_regs) > + return; > + > + while (!takedown_complete && nretry) { > + nretry--; > + > + regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5, > + QACCEPT_TIMEOUT_US); > + > + regmap_write(map, offset + QACCEPT_REQ_REG, 0); > + > + retry = 10; > + while (retry) { > + usleep_range(5, 10); > + retry--; > + ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val); > + if (!ret && val) { > + regmap_write(map, offset + QACCEPT_REQ_REG, 1); > + break; > + } > + > + ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val); > + if (!ret && !val) { > + takedown_complete = true; > + break; > + } A bit of commentary in this branch would do no harm. From the code flow I can guess that disabling the channel failed when QACCEPT_DENY_REG != 0, and hence the channel is re-enabled (?) for the next try, and apparently things are fine when QACCEPT_ACCEPT_REG is 0 after disabling the channel. Would be good to be a bit more explicit about what all that actually means. > + } > + > + if (!retry) > + break; > + } > + > + if (!takedown_complete) > + dev_err(qproc->dev, "qchannel takedown failed\n"); > +}
Hey Matthias, Thanks for taking time to review the patch series. On 2021-06-25 06:05, Matthias Kaehlcke wrote: > Hi Sibi, > > On Fri, Jun 25, 2021 at 01:17:34AM +0530, Sibi Sankar wrote: >> Add out of reset sequence support for modem sub-system on SC7280 SoCs. >> It requires access to an additional set of qaccept registers, external >> power/clk control registers and halt vq6 register to put the modem >> back >> into reset. >> >> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> >> --- >> drivers/remoteproc/qcom_q6v5_mss.c | 245 >> ++++++++++++++++++++++++++++++++++++- >> 1 file changed, 241 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/remoteproc/qcom_q6v5_mss.c >> b/drivers/remoteproc/qcom_q6v5_mss.c >> index 5d21084004cb..4e32811e0025 100644 >> --- a/drivers/remoteproc/qcom_q6v5_mss.c >> +++ b/drivers/remoteproc/qcom_q6v5_mss.c >> @@ -77,6 +77,14 @@ >> >> #define HALT_ACK_TIMEOUT_US 100000 >> >> +/* QACCEPT Register Offsets */ >> +#define QACCEPT_ACCEPT_REG 0x0 >> +#define QACCEPT_ACTIVE_REG 0x4 >> +#define QACCEPT_DENY_REG 0x8 >> +#define QACCEPT_REQ_REG 0xC >> + >> +#define QACCEPT_TIMEOUT_US 50 >> + >> /* QDSP6SS_RESET */ >> #define Q6SS_STOP_CORE BIT(0) >> #define Q6SS_CORE_ARES BIT(1) >> @@ -143,6 +151,9 @@ struct rproc_hexagon_res { >> bool has_alt_reset; >> bool has_mba_logs; >> bool has_spare_reg; >> + bool has_qaccept_regs; >> + bool has_ext_cntl_regs; >> + bool has_vq6; >> }; >> >> struct q6v5 { >> @@ -158,8 +169,18 @@ struct q6v5 { >> u32 halt_q6; >> u32 halt_modem; >> u32 halt_nc; >> + u32 halt_vq6; >> u32 conn_box; >> >> + u32 qaccept_mdm; >> + u32 qaccept_cx; >> + u32 qaccept_axi; >> + >> + u32 axim1_clk_off; >> + u32 crypto_clk_off; >> + u32 force_clk_on; >> + u32 rscc_disable; >> + >> struct reset_control *mss_restart; >> struct reset_control *pdc_reset; >> >> @@ -201,6 +222,9 @@ struct q6v5 { >> bool has_alt_reset; >> bool has_mba_logs; >> bool has_spare_reg; >> + bool has_qaccept_regs; >> + bool has_ext_cntl_regs; >> + bool has_vq6; >> int mpss_perm; >> int mba_perm; >> const char *hexagon_mdt_image; >> @@ -213,6 +237,7 @@ enum { >> MSS_MSM8996, >> MSS_MSM8998, >> MSS_SC7180, >> + MSS_SC7280, >> MSS_SDM845, >> }; >> >> @@ -473,6 +498,12 @@ static int q6v5_reset_assert(struct q6v5 *qproc) >> regmap_update_bits(qproc->conn_map, qproc->conn_box, >> AXI_GATING_VALID_OVERRIDE, 0); >> ret = reset_control_deassert(qproc->mss_restart); >> + } else if (qproc->has_ext_cntl_regs) { >> + regmap_write(qproc->conn_map, qproc->rscc_disable, 0); >> + reset_control_assert(qproc->pdc_reset); >> + reset_control_assert(qproc->mss_restart); >> + reset_control_deassert(qproc->pdc_reset); >> + ret = reset_control_deassert(qproc->mss_restart); >> } else { >> ret = reset_control_assert(qproc->mss_restart); >> } >> @@ -490,7 +521,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc) >> ret = reset_control_reset(qproc->mss_restart); >> writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); >> reset_control_deassert(qproc->pdc_reset); >> - } else if (qproc->has_spare_reg) { >> + } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) { >> ret = reset_control_reset(qproc->mss_restart); >> } else { >> ret = reset_control_deassert(qproc->mss_restart); >> @@ -604,7 +635,7 @@ static int q6v5proc_reset(struct q6v5 *qproc) >> } >> >> goto pbl_wait; >> - } else if (qproc->version == MSS_SC7180) { >> + } else if (qproc->version == MSS_SC7180 || qproc->version == >> MSS_SC7280) { >> val = readl(qproc->reg_base + QDSP6SS_SLEEP); >> val |= Q6SS_CBCR_CLKEN; >> writel(val, qproc->reg_base + QDSP6SS_SLEEP); >> @@ -787,6 +818,82 @@ static int q6v5proc_reset(struct q6v5 *qproc) >> return ret; >> } >> >> +static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap >> *map, u32 offset) >> +{ >> + unsigned int val; >> + int ret; >> + >> + if (!qproc->has_qaccept_regs) >> + return 0; >> + >> + if (qproc->has_ext_cntl_regs) { >> + regmap_write(qproc->conn_map, qproc->rscc_disable, 0); >> + regmap_write(qproc->conn_map, qproc->force_clk_on, 1); >> + >> + ret = regmap_read_poll_timeout(qproc->halt_map, >> qproc->axim1_clk_off, val, >> + !val, 1, Q6SS_CBCR_TIMEOUT_US); >> + if (ret) { >> + dev_err(qproc->dev, "failed to enable axim1 clock\n"); >> + return -ETIMEDOUT; >> + } >> + } >> + >> + regmap_write(map, offset + QACCEPT_REQ_REG, 1); >> + >> + /* Wait for accept */ >> + ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, >> val, val, 5, >> + QACCEPT_TIMEOUT_US); >> + if (ret) { >> + dev_err(qproc->dev, "qchannel enable failed\n"); >> + return -ETIMEDOUT; >> + } >> + >> + return 0; >> +} >> + >> +static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct >> regmap *map, u32 offset) >> +{ >> + int ret; >> + unsigned int val, retry; >> + unsigned int nretry = 10; >> + bool takedown_complete = false; >> + >> + if (!qproc->has_qaccept_regs) >> + return; >> + >> + while (!takedown_complete && nretry) { >> + nretry--; >> + >> + regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, >> !val, 5, >> + QACCEPT_TIMEOUT_US); >> + >> + regmap_write(map, offset + QACCEPT_REQ_REG, 0); Sure I'll add more comments to this func. After lowering the request ^^ we wait for deny to go high or accept to go low. If it's the former then we do a request high and repeat the entire process again. If it's the latter then its considered that the takedown is success. Let me know if you feel any other parts of the patch requires more comments as well. >> + >> + retry = 10; >> + while (retry) { >> + usleep_range(5, 10); >> + retry--; >> + ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val); >> + if (!ret && val) { >> + regmap_write(map, offset + QACCEPT_REQ_REG, 1); >> + break; >> + } >> + >> + ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val); >> + if (!ret && !val) { >> + takedown_complete = true; >> + break; >> + } > > A bit of commentary in this branch would do no harm. From the code flow > I can guess that disabling the channel failed when QACCEPT_DENY_REG != > 0, > and hence the channel is re-enabled (?) for the next try, and > apparently > things are fine when QACCEPT_ACCEPT_REG is 0 after disabling the > channel. > Would be good to be a bit more explicit about what all that actually > means. > >> + } >> + >> + if (!retry) >> + break; >> + } >> + >> + if (!takedown_complete) >> + dev_err(qproc->dev, "qchannel takedown failed\n"); >> +}
On Fri, Jun 25, 2021 at 01:17:30AM +0530, Sibi Sankar wrote: > Add MPSS PAS support for SC7280 SoCs. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> On which tree is this series based? I guess it must be the remoteproc tree since the conversion of the binding to YAML isn't in Linus' tree yet, however the patch doesn't apply cleanly against remoteproc/for-next: patching file Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml Hunk #2 succeeded at 144 (offset -4 lines). Hunk #3 succeeded at 285 (offset -4 lines). Hunk #4 succeeded at 416 with fuzz 2 (offset 23 lines). Hunk #5 succeeded at 492 (offset 25 lines). Hunk #6 FAILED at 485.
On 2021-06-25 22:42, Matthias Kaehlcke wrote: > On Fri, Jun 25, 2021 at 01:17:30AM +0530, Sibi Sankar wrote: >> Add MPSS PAS support for SC7280 SoCs. >> >> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > > On which tree is this series based? I guess it must be the remoteproc > tree > since the conversion of the binding to YAML isn't in Linus' tree yet, > however the patch doesn't apply cleanly against remoteproc/for-next: > > patching file > Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml > Hunk #2 succeeded at 144 (offset -4 lines). > Hunk #3 succeeded at 285 (offset -4 lines). > Hunk #4 succeeded at 416 with fuzz 2 (offset 23 lines). > Hunk #5 succeeded at 492 (offset 25 lines). > Hunk #6 FAILED at 485. https://patchwork.kernel.org/project/linux-arm-msm/cover/1624560727-6870-1-git-send-email-sibis@codeaurora.org/ sry for wasting your time I missed mentioning that it was dependent on ^^ series.
On Fri, Jun 25, 2021 at 10:58:45PM +0530, Sibi Sankar wrote: > On 2021-06-25 22:42, Matthias Kaehlcke wrote: > > On Fri, Jun 25, 2021 at 01:17:30AM +0530, Sibi Sankar wrote: > > > Add MPSS PAS support for SC7280 SoCs. > > > > > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > > > > On which tree is this series based? I guess it must be the remoteproc > > tree > > since the conversion of the binding to YAML isn't in Linus' tree yet, > > however the patch doesn't apply cleanly against remoteproc/for-next: > > > > patching file > > Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml > > Hunk #2 succeeded at 144 (offset -4 lines). > > Hunk #3 succeeded at 285 (offset -4 lines). > > Hunk #4 succeeded at 416 with fuzz 2 (offset 23 lines). > > Hunk #5 succeeded at 492 (offset 25 lines). > > Hunk #6 FAILED at 485. > > https://patchwork.kernel.org/project/linux-arm-msm/cover/1624560727-6870-1-git-send-email-sibis@codeaurora.org/ > > sry for wasting your time I missed > mentioning that it was dependent on > ^^ series. Ah, thanks! Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
On Fri, Jun 25, 2021 at 01:17:35AM +0530, Sibi Sankar wrote: > Subject: arm64: dts: qcom: sc7280: Update reserved memory map That's very vague. Also personally I'm not a fan of patches that touch SoC and board files with a commit message that only mentions the SoC, as is frequently done for IDP boards. Why not split this in (at least) two, one for adding the missing memory regions to the SoC, and one for the IDP. > Add missing regions and remove unused regions from the reserved memory > map, as described in version 1. What is this 'version 1'?
On Fri, Jun 25, 2021 at 01:17:38AM +0530, Sibi Sankar wrote: > Update MSS node to support MSA based modem boot on SC7280 SoCs. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 7 +++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 ++++++++++++++++--- > 2 files changed, 23 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > index 191e8a92d153..d66e3ca42ad5 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > @@ -343,3 +343,10 @@ > bias-pull-up; > }; > }; > + > +&remoteproc_mpss { > + status = "okay"; > + compatible = "qcom,sc7280-mss-pil"; > + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; > + memory-region = <&mba_mem &mpss_mem>; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 56ea172f641f..6d3687744440 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -586,7 +586,8 @@ > > remoteproc_mpss: remoteproc@4080000 { > compatible = "qcom,sc7280-mpss-pas"; > - reg = <0 0x04080000 0 0x10000>; > + reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; > + reg-names = "qdsp6", "rmb"; Binding needs update? Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml: reg: maxItems: 1 > > interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, > <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > @@ -597,8 +598,11 @@ > interrupt-names = "wdog", "fatal", "ready", "handover", > "stop-ack", "shutdown-ack"; > > - clocks = <&rpmhcc RPMH_CXO_CLK>; > - clock-names = "xo"; > + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, > + <&gcc GCC_MSS_OFFLINE_AXI_CLK>, > + <&gcc GCC_MSS_SNOC_AXI_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "offline", "snoc_axi", "xo"; Binding needs update? Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml: clocks: items: - description: XO clock clock-names: items: - const: xo
On 2021-06-29 00:35, Matthias Kaehlcke wrote: > On Fri, Jun 25, 2021 at 01:17:38AM +0530, Sibi Sankar wrote: >> Update MSS node to support MSA based modem boot on SC7280 SoCs. >> >> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 7 +++++++ >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 ++++++++++++++++--- >> 2 files changed, 23 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts >> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts >> index 191e8a92d153..d66e3ca42ad5 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts >> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts >> @@ -343,3 +343,10 @@ >> bias-pull-up; >> }; >> }; >> + >> +&remoteproc_mpss { >> + status = "okay"; >> + compatible = "qcom,sc7280-mss-pil"; >> + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; >> + memory-region = <&mba_mem &mpss_mem>; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 56ea172f641f..6d3687744440 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -586,7 +586,8 @@ >> >> remoteproc_mpss: remoteproc@4080000 { >> compatible = "qcom,sc7280-mpss-pas"; >> - reg = <0 0x04080000 0 0x10000>; >> + reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; >> + reg-names = "qdsp6", "rmb"; > > Binding needs update? > > Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml: > > reg: > maxItems: 1 > >> >> interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, >> <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, >> @@ -597,8 +598,11 @@ >> interrupt-names = "wdog", "fatal", "ready", "handover", >> "stop-ack", "shutdown-ack"; >> >> - clocks = <&rpmhcc RPMH_CXO_CLK>; >> - clock-names = "xo"; >> + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, >> + <&gcc GCC_MSS_OFFLINE_AXI_CLK>, >> + <&gcc GCC_MSS_SNOC_AXI_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", "offline", "snoc_axi", "xo"; > > Binding needs update? > > Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml: > > clocks: > items: > - description: XO clock > clock-names: > items: > - const: xo qcom,sc7280-mpss-pas compatible requires just the xo clock and one reg space whereas the qcom,sc7280-mss-pil compatible requires the additional clks and reg spaces. We just overload properties where re-use is possible across boards. Hence it would be wrong to list those clks/reg spaces as requirements for the pas compatible. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
Hi! > This patch series adds support for booting the Modem Q6 DSP found on > Qualcomm's SC7280 SoCs. Am I right this is phone related? Can I get you to cc phone-devel mailing list? Best regards, Pavel
On Fri, 25 Jun 2021 01:17:30 +0530, Sibi Sankar wrote: > Add MPSS PAS support for SC7280 SoCs. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > --- > Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Wed 30 Jun 15:08 CDT 2021, Sibi Sankar wrote: > On 2021-06-29 00:35, Matthias Kaehlcke wrote: > > On Fri, Jun 25, 2021 at 01:17:38AM +0530, Sibi Sankar wrote: > > > Update MSS node to support MSA based modem boot on SC7280 SoCs. > > > > > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > > > --- > > > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 7 +++++++ > > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 ++++++++++++++++--- > > > 2 files changed, 23 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > > > b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > > > index 191e8a92d153..d66e3ca42ad5 100644 > > > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > > > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > > > @@ -343,3 +343,10 @@ > > > bias-pull-up; > > > }; > > > }; > > > + > > > +&remoteproc_mpss { > > > + status = "okay"; > > > + compatible = "qcom,sc7280-mss-pil"; > > > + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; > > > + memory-region = <&mba_mem &mpss_mem>; > > > +}; > > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > b/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > index 56ea172f641f..6d3687744440 100644 > > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > > > @@ -586,7 +586,8 @@ > > > > > > remoteproc_mpss: remoteproc@4080000 { > > > compatible = "qcom,sc7280-mpss-pas"; > > > - reg = <0 0x04080000 0 0x10000>; > > > + reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; > > > + reg-names = "qdsp6", "rmb"; > > > > Binding needs update? > > > > Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml: > > > > reg: > > maxItems: 1 > > > > > > > > interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, > > > <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > > > @@ -597,8 +598,11 @@ > > > interrupt-names = "wdog", "fatal", "ready", "handover", > > > "stop-ack", "shutdown-ack"; > > > > > > - clocks = <&rpmhcc RPMH_CXO_CLK>; > > > - clock-names = "xo"; > > > + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, > > > + <&gcc GCC_MSS_OFFLINE_AXI_CLK>, > > > + <&gcc GCC_MSS_SNOC_AXI_CLK>, > > > + <&rpmhcc RPMH_CXO_CLK>; > > > + clock-names = "iface", "offline", "snoc_axi", "xo"; > > > > Binding needs update? > > > > Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml: > > > > clocks: > > items: > > - description: XO clock > > clock-names: > > items: > > - const: xo > > qcom,sc7280-mpss-pas compatible requires > just the xo clock and one reg space whereas > the qcom,sc7280-mss-pil compatible requires > the additional clks and reg spaces. We just > overload properties where re-use is possible > across boards. Hence it would be wrong to > list those clks/reg spaces as requirements > for the pas compatible. > Our decision to describe the platform node as a superset of the resources needed by the pas and pil variants was never reflected in the DT bindings; resulting in the issue that the superset doesn't validate against the pas binding and both bindings are full of platform-specific conditionals. To resolve the two issues I think we should split the current binding(s) in a set of platform-centric bindings, that captures the idea of describing the superset. To reduce the duplication - that already exists between the two bindings - I think we should break those out in a common part. I'm however fine with not delaying this series further, if we agree that the end result matches what we would put in a combined qcom,sc7280-mpss binding. Regards, Bjorn