From patchwork Tue Jun 24 14:49:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 32427 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f71.google.com (mail-oa0-f71.google.com [209.85.219.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0172A203AC for ; Tue, 24 Jun 2014 14:52:00 +0000 (UTC) Received: by mail-oa0-f71.google.com with SMTP id n16sf2085584oag.6 for ; Tue, 24 Jun 2014 07:52:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:date:from:to:subject:in-reply-to :message-id:references:user-agent:mime-version:cc:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :sender:errors-to:x-original-sender :x-original-authentication-results:mailing-list:content-type :content-transfer-encoding; bh=TmEP1WeHwj2iSrLS/cZXCCpbxbmttxxT1qaDHQ7HoJ4=; b=bIc9W6nZBbVNCmWzCUTy5QSh/TsDpomLhUR0c3tpv5kDsCkNb1Jcs8EszTchiRaX1c 1g49PBVmV5cS9EPYLqlJEmYwxZ+T3MgZ1yW/eeYTcFKcF4EzC/etmLwGWn+4PDBS3Wj5 CahchE+CUUs4VJgbV8diUn4c1QB5FUfG2zSaPmSLEvOCoWAJoXHeGZhblgiiZr8yYuyv nShBpHHkkpCjBqE2I2A7cJrmKswwdFGLUsb0EziV/UDDjJ2NRMT7wToexZE1Js2c+N8u QSRAaGt+MGIUYSOxKfQ2T2uPxKcyKXxQT/Hm29c0cLw1Jd2cd/+O7Fe2WfHK0TkGMIQW NP/Q== X-Gm-Message-State: ALoCoQmZtUnuMVj1d+Ly4WPDq9FLGWBxvQvvSiGoiqEmuh+Q3xf8zDeSVXayDkPh19IuR/9o65j2 X-Received: by 10.182.66.198 with SMTP id h6mr738599obt.12.1403621520526; Tue, 24 Jun 2014 07:52:00 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.94.100 with SMTP id f91ls2461375qge.65.gmail; Tue, 24 Jun 2014 07:52:00 -0700 (PDT) X-Received: by 10.220.164.198 with SMTP id f6mr1088939vcy.51.1403621520410; Tue, 24 Jun 2014 07:52:00 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id qe9si320225vcb.79.2014.06.24.07.52.00 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 24 Jun 2014 07:52:00 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id hy4so433563vcb.19 for ; Tue, 24 Jun 2014 07:52:00 -0700 (PDT) X-Received: by 10.221.26.10 with SMTP id rk10mr1214122vcb.0.1403621520324; Tue, 24 Jun 2014 07:52:00 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp217078vcb; Tue, 24 Jun 2014 07:51:59 -0700 (PDT) X-Received: by 10.140.94.225 with SMTP id g88mr2072462qge.101.1403621519763; Tue, 24 Jun 2014 07:51:59 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id u6si636577qae.106.2014.06.24.07.51.59 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Jun 2014 07:51:59 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WzS2q-0001ut-6W; Tue, 24 Jun 2014 14:50:00 +0000 Received: from mail-qg0-f48.google.com ([209.85.192.48]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WzS2c-0001Su-LU for linux-arm-kernel@lists.infradead.org; Tue, 24 Jun 2014 14:49:48 +0000 Received: by mail-qg0-f48.google.com with SMTP id q108so360425qgd.35 for ; Tue, 24 Jun 2014 07:49:24 -0700 (PDT) X-Received: by 10.140.85.102 with SMTP id m93mr2468593qgd.26.1403621364670; Tue, 24 Jun 2014 07:49:24 -0700 (PDT) Received: from xanadu.home (modemcable177.143-130-66.mc.videotron.ca. [66.130.143.177]) by mx.google.com with ESMTPSA id c52sm298602qgc.32.2014.06.24.07.49.23 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 24 Jun 2014 07:49:24 -0700 (PDT) Date: Tue, 24 Jun 2014 10:49:23 -0400 (EDT) From: Nicolas Pitre To: Catalin Marinas Subject: Re: VFP handling in multiplatform feroceon kernels In-Reply-To: <20140624141056.GD4489@arm.com> Message-ID: References: <7416978.W29blLsymn@wuerfel> <20140624134249.GB4489@arm.com> <20140624141056.GD4489@arm.com> User-Agent: Alpine 2.11 (LFD 23 2013-08-11) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140624_074946_791941_AAE7CC2F X-CRM114-Status: GOOD ( 25.44 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.192.48 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.48 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record Cc: Andrew Lunn , Jason Cooper , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" , Russell King , Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: nicolas.pitre@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On Tue, 24 Jun 2014, Catalin Marinas wrote: > On Tue, Jun 24, 2014 at 03:04:14PM +0100, Nicolas Pitre wrote: > > On Tue, 24 Jun 2014, Catalin Marinas wrote: > > > > > On Tue, Jun 24, 2014 at 02:17:06PM +0100, Arnd Bergmann wrote: > > > > Since 3.16, we have the ability to build a multiplatform kernel > > > > that includes both kirkwood (feroceon) and some other ARMv5 CPU. > > > > > > > > I accidentally stumbled over a bug in the VFP code that looks > > > > like it will break at least ARM9 VFP support if CPU_FEROCEON > > > > is also enabled, introduced by this (old) commit: > > > > > > I would argue that the bug is in the CPU (feroceon). See the end of this > > > email: > > > > > > http://www.spinics.net/lists/arm-kernel/msg41460.html > > > > > > and my follow-up. Basically you can't avoid the conditional compilation > > > as Feroceon doesn't follow the VFP sub-architecture spec and doesn't > > > present itself as a different CPU from an _ARM_ 9. Unless things have > > > changed with Marvell's hardware implementation and they got a new id, I > > > suggest you don't enable this for multi-platform. > > > > Only the early revision did hijack the ARM9 ID but still. We certainly > > can determine at run time if the platform being booted is equiped with a > > Feroceon before user space is started. In that case I'd suggest some > > runtime code patching to branch to some out-of-line assembly code for > > Feroceon. > > You don't even need to branch to out of line assembly, just branch over > the imprecise VFP abort handling in arch/arm/vfp/vfphw.S. Even better. I looked too quickly at the patch seeing a #ifdef while it is in fact #ifndef. What about something like this? Then suffice to call vfp_feroceon_quirk() during boot when appropriate. Nicolas diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index be807625ed..d46eb84884 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -115,7 +115,7 @@ ENTRY(vfp_support_entry) beq vfp_reload_hw @ then the hw state needs reloading VFPFSTMIA r4, r5 @ save the working registers VFPFMRX r5, FPSCR @ current status -#ifndef CONFIG_CPU_FEROCEON +vfp_extra: tst r1, #FPEXC_EX @ is there additional state to save? beq 1f VFPFMRX r6, FPINST @ FPINST (only if FPEXC.EX is set) @@ -123,7 +123,6 @@ ENTRY(vfp_support_entry) beq 1f VFPFMRX r8, FPINST2 @ FPINST2 if needed (and present) 1: -#endif stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2 vfp_reload_hw: @@ -219,6 +218,19 @@ process_exception: @ retry the faulted instruction ENDPROC(vfp_support_entry) +#ifdef CONFIG_CPU_FEROCEON +ENTRY(vfp_feroceon_quirk) + /* force a skip over the imprecise VFP abort handling */ + adr r0, vfp_extra + ldr r1, .L_eq_insn + str r1, [r0] + add r1, r0, #4 + b feroceon_coherent_kern_range +.L_eq_insn: + teq r0, r0 +ENDPROC(vfp_feroceon_quirk) +#endif + ENTRY(vfp_save_state) @ Save the current VFP state @ r0 - save location