From patchwork Mon Jan 20 15:32:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 23407 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ig0-f200.google.com (mail-ig0-f200.google.com [209.85.213.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 646EB203C6 for ; Mon, 20 Jan 2014 15:34:09 +0000 (UTC) Received: by mail-ig0-f200.google.com with SMTP id k19sf14084891igc.3 for ; Mon, 20 Jan 2014 07:34:08 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:date:from:to:cc:subject:in-reply-to :message-id:references:user-agent:mime-version:sender:precedence :list-id:x-original-sender:x-original-authentication-results :mailing-list:list-post:list-help:list-archive:list-unsubscribe :content-type; bh=/XrFzFaAciS9dlcJz3nt+5Tq/F4e7V0EWsAfJsRTJmI=; b=B/oiGltTXOBaD9aRRBlqS7fbJanaMJabcbtwVV4F2a0ATbrLA3/xRVJ5eUU5rPExk7 da0iBnJ9jkIx/rPWizAt+9Iga+CRZoxzVftl25BLM9yvmWEZCOmqyB26RAOCUrEYJQyZ 8kdRyQEfXm9cFSqpZbr27QuAenExYgT6DoiETTdISLzUYwse7Kh9uhve16dkPWuSza8r n4RaPhVq48Qr7JQn/G8MIAth/dgjpjkfBNYdMQm4dHRksR7lA1eeS3A/TqWmt6/q4Mo9 S2KnQjED0voZXj6Hgc6kfXjU1J1pfVgNrEXfqxrQwO8ai3E/6KmjTRBxOwoqzDqSB6yW WDCQ== X-Gm-Message-State: ALoCoQmSxtGwpNAyLkSS0EZX23EAZpqrZBn2oKseiCMPMqbDLwG4H4tPs1+iRytL/yYgZhLBof0v X-Received: by 10.182.87.2 with SMTP id t2mr7061180obz.2.1390232048643; Mon, 20 Jan 2014 07:34:08 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.110.197 with SMTP id ic5ls669533qeb.58.gmail; Mon, 20 Jan 2014 07:34:08 -0800 (PST) X-Received: by 10.58.117.65 with SMTP id kc1mr30172veb.68.1390232048531; Mon, 20 Jan 2014 07:34:08 -0800 (PST) Received: from mail-ve0-f173.google.com (mail-ve0-f173.google.com [209.85.128.173]) by mx.google.com with ESMTPS id x5si453229veb.111.2014.01.20.07.34.08 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 20 Jan 2014 07:34:08 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.173; Received: by mail-ve0-f173.google.com with SMTP id oz11so1813876veb.32 for ; Mon, 20 Jan 2014 07:34:08 -0800 (PST) X-Received: by 10.52.74.99 with SMTP id s3mr46276vdv.42.1390232048420; Mon, 20 Jan 2014 07:34:08 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.174.196 with SMTP id u4csp63507vcz; Mon, 20 Jan 2014 07:34:07 -0800 (PST) X-Received: by 10.68.231.35 with SMTP id td3mr3995028pbc.137.1390232047185; Mon, 20 Jan 2014 07:34:07 -0800 (PST) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id to9si1864980pbc.155.2014.01.20.07.34.06; Mon, 20 Jan 2014 07:34:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753150AbaATPeB (ORCPT + 26 others); Mon, 20 Jan 2014 10:34:01 -0500 Received: from smtp.citrix.com ([66.165.176.89]:6209 "EHLO SMTP.CITRIX.COM" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751669AbaATPd5 (ORCPT ); Mon, 20 Jan 2014 10:33:57 -0500 X-IronPort-AV: E=Sophos;i="4.95,691,1384300800"; d="scan'208";a="94525667" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 20 Jan 2014 15:33:53 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.2.342.4; Mon, 20 Jan 2014 10:33:53 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1W5GrI-0008W5-1C; Mon, 20 Jan 2014 15:33:52 +0000 Date: Mon, 20 Jan 2014 15:32:48 +0000 From: Stefano Stabellini X-X-Sender: sstabellini@kaball.uk.xensource.com To: Will Deacon CC: Stefano Stabellini , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" , "linux@arm.linux.org.uk" , Catalin Marinas , "gang.chen@asianux.com" , "linux-kernel@vger.kernel.org" , "jaccon.bastiaansen@gmail.com" Subject: Re: [PATCH v3] arm: remove !CPU_V6 and !GENERIC_ATOMIC64 build dependencies for XEN In-Reply-To: <20140116193123.GB22105@mudshark.cambridge.arm.com> Message-ID: References: <1389204023-26912-1-git-send-email-stefano.stabellini@eu.citrix.com> <20140109103004.GB11089@mudshark.cambridge.arm.com> <201401091204.17932.arnd@arndb.de> <20140109184251.GL17838@mudshark.cambridge.arm.com> <20140116193123.GB22105@mudshark.cambridge.arm.com> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 X-DLP: MIA2 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On Thu, 16 Jan 2014, Will Deacon wrote: > Hi Stefano, > > On Thu, Jan 16, 2014 at 04:27:55PM +0000, Stefano Stabellini wrote: > > On Thu, 9 Jan 2014, Will Deacon wrote: > > > Ok, thanks for the explanation. Looking at the patch, I wonder whether it's > > > not cleaner just to implement xchg code separately for Xen? The Linux code > > > isn't always sufficient (due to the GENERIC_ATOMIC64 stuff) and most of the > > > churn coming out of this patch is an attempt to provide some small code > > > reuse at the cost of code readability. > > > > > > What do others think? > > > > I am OK with that, in fact my first version of the patch did just that: > > > > http://marc.info/?l=linux-arm-kernel&m=138436406724990&w=2 > > > > Is that what you had in mind? > > For the xchg part, yes, that looks a lot better. I don't like the #undef > CONFIG_CPU_V6 though, can that be rewritten to use __LINUX_ARM_ARCH__? The problem is that the 1 and 2 byte parameter size cases in __cmpxchg are ifdef'ed CONFIG_CPU_V6 but drivers/xen/grant-table.c needs them. So we can either undef CONFIG_CPU_V6 in grant-table.c or call a different function. If I switch from ifdef CONFIG_CPU_V6 to if __LINUX_ARM_ARCH__ > 6 in __cmpxchg, we still have the problem that if __LINUX_ARM_ARCH__ == 6, grant-table.c doesn't compile. Maybe the approach taken by the other patch for cmpxchg is better, see below. --- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c1f1a7e..ae54ae0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1881,8 +1881,7 @@ config XEN_DOM0 config XEN bool "Xen guest support on ARM (EXPERIMENTAL)" depends on ARM && AEABI && OF - depends on CPU_V7 && !CPU_V6 - depends on !GENERIC_ATOMIC64 + depends on CPU_V7 select ARM_PSCI select SWIOTLB_XEN help diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index df2fbba..cc8a4a2 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -133,6 +133,44 @@ extern void __bad_cmpxchg(volatile void *ptr, int size); * cmpxchg only support 32-bits operands on ARMv6. */ +static inline unsigned long __cmpxchg8(volatile void *ptr, unsigned long old, + unsigned long new) +{ + unsigned long oldval, res; + + do { + asm volatile("@ __cmpxchg1\n" + " ldrexb %1, [%2]\n" + " mov %0, #0\n" + " teq %1, %3\n" + " strexbeq %0, %4, [%2]\n" + : "=&r" (res), "=&r" (oldval) + : "r" (ptr), "Ir" (old), "r" (new) + : "memory", "cc"); + } while (res); + + return oldval; +} + +static inline unsigned long __cmpxchg16(volatile void *ptr, unsigned long old, + unsigned long new) +{ + unsigned long oldval, res; + + do { + asm volatile("@ __cmpxchg1\n" + " ldrexh %1, [%2]\n" + " mov %0, #0\n" + " teq %1, %3\n" + " strexheq %0, %4, [%2]\n" + : "=&r" (res), "=&r" (oldval) + : "r" (ptr), "Ir" (old), "r" (new) + : "memory", "cc"); + } while (res); + + return oldval; +} + static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) { @@ -141,28 +179,10 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, switch (size) { #ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */ case 1: - do { - asm volatile("@ __cmpxchg1\n" - " ldrexb %1, [%2]\n" - " mov %0, #0\n" - " teq %1, %3\n" - " strexbeq %0, %4, [%2]\n" - : "=&r" (res), "=&r" (oldval) - : "r" (ptr), "Ir" (old), "r" (new) - : "memory", "cc"); - } while (res); + oldval = __cmpxchg8(ptr, old, new); break; case 2: - do { - asm volatile("@ __cmpxchg1\n" - " ldrexh %1, [%2]\n" - " mov %0, #0\n" - " teq %1, %3\n" - " strexheq %0, %4, [%2]\n" - : "=&r" (res), "=&r" (oldval) - : "r" (ptr), "Ir" (old), "r" (new) - : "memory", "cc"); - } while (res); + oldval = __cmpxchg16(ptr, old, new); break; #endif case 4: diff --git a/arch/arm/include/asm/sync_bitops.h b/arch/arm/include/asm/sync_bitops.h index 63479ee..942659a 100644 --- a/arch/arm/include/asm/sync_bitops.h +++ b/arch/arm/include/asm/sync_bitops.h @@ -21,7 +21,29 @@ #define sync_test_and_clear_bit(nr, p) _test_and_clear_bit(nr, p) #define sync_test_and_change_bit(nr, p) _test_and_change_bit(nr, p) #define sync_test_bit(nr, addr) test_bit(nr, addr) -#define sync_cmpxchg cmpxchg +static inline unsigned long sync_cmpxchg(volatile void *ptr, + unsigned long old, + unsigned long new) +{ + unsigned long oldval; + int size = sizeof(*(ptr)); + + smp_mb(); + switch (size) { + case 1: + oldval = __cmpxchg8(ptr, old, new); + break; + case 2: + oldval = __cmpxchg16(ptr, old, new); + break; + default: + oldval = __cmpxchg(ptr, old, new, size); + break; + } + smp_mb(); + + return oldval; +} #endif diff --git a/arch/arm/include/asm/xen/events.h b/arch/arm/include/asm/xen/events.h index 8b1f37b..2032ee6 100644 --- a/arch/arm/include/asm/xen/events.h +++ b/arch/arm/include/asm/xen/events.h @@ -16,7 +16,37 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) return raw_irqs_disabled_flags(regs->ARM_cpsr); } -#define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr), \ +#ifdef CONFIG_GENERIC_ATOMIC64 +/* if CONFIG_GENERIC_ATOMIC64 is defined we cannot use the generic + * atomic64_xchg function because it is implemented using spin locks. + * Here we need proper atomic instructions to read and write memory + * shared with the hypervisor. + */ +static inline u64 xen_atomic64_xchg(atomic64_t *ptr, u64 new) +{ + u64 result; + unsigned long tmp; + + smp_mb(); + + __asm__ __volatile__("@ xen_atomic64_xchg\n" +"1: ldrexd %0, %H0, [%3]\n" +" strexd %1, %4, %H4, [%3]\n" +" teq %1, #0\n" +" bne 1b" + : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter) + : "r" (&ptr->counter), "r" (new) + : "cc"); + + smp_mb(); + + return result; +} +#else +#define xen_atomic64_xchg atomic64_xchg +#endif + +#define xchg_xen_ulong(ptr, val) xen_atomic64_xchg(container_of((ptr), \ atomic64_t, \ counter), (val))