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[2001:1868:205::9]) by mx.google.com with ESMTPS id ag4si1068729pac.77.2014.08.06.07.39.26 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Aug 2014 07:39:26 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XF2MH-00006U-84; Wed, 06 Aug 2014 14:38:29 +0000 Received: from mail-la0-f44.google.com ([209.85.215.44]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XF2MF-0008NB-1R for linux-arm-kernel@lists.infradead.org; Wed, 06 Aug 2014 14:38:27 +0000 Received: by mail-la0-f44.google.com with SMTP id el20so1078588lab.31 for ; Wed, 06 Aug 2014 07:38:04 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.112.16.230 with SMTP id j6mr11076685lbd.90.1407335884341; Wed, 06 Aug 2014 07:38:04 -0700 (PDT) Received: by 10.112.247.70 with HTTP; Wed, 6 Aug 2014 07:38:04 -0700 (PDT) In-Reply-To: <20140806143430.GU25953@arm.com> References: <1407230757-15305-1-git-send-email-ard.biesheuvel@linaro.org> <1407230757-15305-2-git-send-email-ard.biesheuvel@linaro.org> <20140806130026.GR25953@arm.com> <20140806143430.GU25953@arm.com> Date: Wed, 6 Aug 2014 16:38:04 +0200 Message-ID: Subject: Re: [PATCH v2 2/3] arm64: add helper functions to read I-cache attributes From: Ard Biesheuvel To: Will Deacon X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140806_073827_262223_34BD1587 X-CRM114-Status: GOOD ( 17.28 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.215.44 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.215.44 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Mark Rutland , Catalin Marinas , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ard.biesheuvel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On 6 August 2014 16:34, Will Deacon wrote: > On Wed, Aug 06, 2014 at 02:27:55PM +0100, Ard Biesheuvel wrote: >> On 6 August 2014 15:17, Ard Biesheuvel wrote: >> > On 6 August 2014 15:00, Will Deacon wrote: >> >> On Tue, Aug 05, 2014 at 10:25:56AM +0100, Ard Biesheuvel wrote: >> >>> This adds helper functions and #defines to to read the >> >>> line size and the number of sets from the level 1 instruction cache. >> >>> >> >>> Signed-off-by: Ard Biesheuvel >> >>> --- > > [...] > >> >>> +static inline __attribute_const__ u64 icache_get_ccsidr(void) >> >>> +{ >> >>> + u64 ccsidr; >> >>> + >> >>> + /* Select L1 I-cache and read its size ID register */ >> >>> + asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1" >> >>> + : "=r"(ccsidr) : "r"(1L)); >> >>> + return ccsidr; >> >> >> >> Is it worth having a WARN_ON(preemptible()) here? >> >> >> > >> > Sure, why not. >> >> ... if it weren't for the fact that this triggers recursive header >> inclusion hell >> >> CC kernel/bounds.s >> In file included from /home/ard/linux-2.6/include/asm-generic/preempt.h:4:0, >> from arch/arm64/include/generated/asm/preempt.h:1, >> from /home/ard/linux-2.6/include/linux/preempt.h:18, >> from /home/ard/linux-2.6/arch/arm64/include/asm/cachetype.h:21, > > [...] > >> i.e., linux/bug,h and linux/preempt.h already implicitly #include >> cachetype.h, so including the former from the latter to import the >> declaration of WARN_ON() and/or preemptible respectively produces this >> error. > > Damn, that's a real shame. I'm always dubious about adding code like this > which isn't obviously broken from preemptible context when you're just > looking at the function name. > > Ho-hum. > Moving icache_get_ccsidr() into cpuinfo.c does work, as in the patch below diff --git a/arch/arm64/include/asm/cachetype.h b/arch/arm64/include/asm/cachetype.h index 7a2e0762cb40..4c631a0a3609 100644 --- a/arch/arm64/include/asm/cachetype.h +++ b/arch/arm64/include/asm/cachetype.h @@ -39,6 +39,26 @@ extern unsigned long __icache_flags; +#define CCSIDR_EL1_LINESIZE_MASK 0x7 +#define CCSIDR_EL1_LINESIZE(x) ((x) & CCSIDR_EL1_LINESIZE_MASK) + +#define CCSIDR_EL1_NUMSETS_SHIFT 13 +#define CCSIDR_EL1_NUMSETS_MASK (0x7fff << CCSIDR_EL1_NUMSETS_SHIFT) +#define CCSIDR_EL1_NUMSETS(x) \ + (((x) & CCSIDR_EL1_NUMSETS_MASK) >> CCSIDR_EL1_NUMSETS_SHIFT) + +extern u64 __attribute_const__ icache_get_ccsidr(void); + +static inline int icache_get_linesize(void) +{ + return 16 << CCSIDR_EL1_LINESIZE(icache_get_ccsidr()); +} + +static inline int icache_get_numsets(void) +{ + return 1 + CCSIDR_EL1_NUMSETS(icache_get_ccsidr()); +} + /* * Whilst the D-side always behaves as PIPT on AArch64, aliasing is * permitted in the I-cache. diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index f798f66634af..319255ff536d 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -20,8 +20,10 @@ #include #include +#include #include #include +#include #include #include @@ -190,3 +192,15 @@ void __init cpuinfo_store_boot_cpu(void) boot_cpu_data = *info; } + +u64 __attribute_const__ icache_get_ccsidr(void) +{ + u64 ccsidr; + + WARN_ON(preemptible()); + + /* Select L1 I-cache and read its size ID register */ + asm("msr csselr_el1, %1; isb; mrs %0, ccsidr_el1" + : "=r"(ccsidr) : "r"(1L)); + return ccsidr; +}