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[2001:1868:205::9]) by mx.google.com with ESMTPS id df3si8340776pbc.99.2014.07.13.22.41.47 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 Jul 2014 22:41:47 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1X6Yzg-0004Of-Qv; Mon, 14 Jul 2014 05:40:08 +0000 Received: from mail-ob0-f177.google.com ([209.85.214.177]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1X6Yze-0003HF-A6 for linux-arm-kernel@lists.infradead.org; Mon, 14 Jul 2014 05:40:06 +0000 Received: by mail-ob0-f177.google.com with SMTP id wp18so3518316obc.8 for ; Sun, 13 Jul 2014 22:39:45 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.123.66 with SMTP id ly2mr15389666oeb.19.1405315907124; Sun, 13 Jul 2014 22:31:47 -0700 (PDT) Received: by 10.182.233.166 with HTTP; Sun, 13 Jul 2014 22:31:47 -0700 (PDT) In-Reply-To: <53BE926A.2070005@ti.com> References: <53BE926A.2070005@ti.com> Date: Mon, 14 Jul 2014 11:01:47 +0530 Message-ID: Subject: Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx From: Viresh Kumar To: Kishon Vijay Abraham I X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140713_224006_411333_B29DF961 X-CRM114-Status: GOOD ( 10.07 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.177 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.214.177 listed in wl.mailspike.net] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders Cc: Pratyush Anand , Bartlomiej Zolnierkiewicz , "linux-pci@vger.kernel.org" , spear-devel , Mark Nicholson , Bjorn Helgaas , "olof@lixom.net" , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: viresh.kumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On 10 July 2014 18:47, Kishon Vijay Abraham I wrote: >> diff --git a/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt >> new file mode 100644 >> index 0000000..b9b281a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt > > We generally create a single document for a SoC vendor. So just use st-phy.txt. st-phy may not be appropriate as this is specifically for SPEAr. New binding doc looks like this: diff --git a/Documentation/devicetree/bindings/phy/st-spear-miphy.txt b/Documentation/devicetree/bindings/phy/st-spear-miphy.txt new file mode 100644 index 0000000..2a6bfdc --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st-spear-miphy.txt @@ -0,0 +1,15 @@ +ST SPEAr miphy DT details +========================= + +ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA. + +Required properties: +- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- #phy-cells : from the generic PHY bindings, must be 1. + - cell[1]: 0 if phy used for SATA, 1 for PCIe. + +Optional properties: +- phy-id: Instance id of the phy. Only required when there are multiple phys + present on a implementation.