From patchwork Wed Jan 4 11:47:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 89916 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp8688342qgi; Wed, 4 Jan 2017 13:45:00 -0800 (PST) X-Received: by 10.84.241.8 with SMTP id a8mr144405444pll.74.1483566300894; Wed, 04 Jan 2017 13:45:00 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id d30si73693147plj.185.2017.01.04.13.45.00 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jan 2017 13:45:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cOtLG-0002RW-0u; Wed, 04 Jan 2017 21:43:30 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cOsqi-0007IB-0r for linux-arm-kernel@bombadil.infradead.org; Wed, 04 Jan 2017 21:11:56 +0000 Received: from foss.arm.com ([217.140.101.70]) by casper.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cOk3H-00022N-FX for linux-arm-kernel@lists.infradead.org; Wed, 04 Jan 2017 11:48:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 82AC5154D; Wed, 4 Jan 2017 03:47:58 -0800 (PST) Received: from [10.1.210.28] (e107155-lin.cambridge.arm.com [10.1.210.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1769F3F242; Wed, 4 Jan 2017 03:47:56 -0800 (PST) From: Sudeep Holla Subject: Re: [QUESTION] Arm64: Query L3 cache info via DT To: Tan Xiaojun References: <58633494.9030708@huawei.com> Organization: ARM Message-ID: <81784854-11f8-468a-a280-69be0a714a3b@arm.com> Date: Wed, 4 Jan 2017 11:47:52 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <58633494.9030708@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170104_114819_844068_EDA518CE X-CRM114-Status: GOOD ( 26.13 ) X-Spam-Score: -10.1 (----------) X-Spam-Report: SpamAssassin version 3.4.1 on casper.infradead.org summary: Content analysis details: (-10.1 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -3.2 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , ard.biesheuvel@linaro.org, Sudeep Holla , linux@armlinux.org.uk, shameerali.kolothum.thodi@huawei.com, Li Zefan , Ding Tianhong , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Hi Tan, On 28/12/16 03:42, Tan Xiaojun wrote: > Hi. > > I saw you discussed how to achieve querying cache information and > tend to implement the external ones(like L3 cache) via DT a few > months ago. > > http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/405399.html > > Are these implementations progressing? Forgive me to take the > liberty to ask, we care about this thing. > Yes the support to override the cache properties for DT was added in v4.10 However, it still depends on the the sysreg to get the total levels of caches supported in the system. You may need to tweak a bit around that to support what you need. > If you've already implemented some codes, we can help with testing > (in Hisilicon D02, D03, D05) after you send it to the mail-list. > Sure, that would help. > We can try our best to help if there is any difficulty. OK, you can start trying the patch below :). It's not even compile tested, so you make have to make some changes necessary. I just wanted to put my thoughts here. Make sure all the L3 cacheinfo is present in DT. Regards, Sudeep -- struct device_node *from, const char *prop_name); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git i/arch/arm64/kernel/cacheinfo.c w/arch/arm64/kernel/cacheinfo.c index 9617301f76b5..88fbcd368104 100644 --- i/arch/arm64/kernel/cacheinfo.c +++ w/arch/arm64/kernel/cacheinfo.c @@ -84,7 +84,7 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, static int __init_cache_level(unsigned int cpu) { - unsigned int ctype, level, leaves; + unsigned int ctype, level, leaves, of_level; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { @@ -97,6 +97,17 @@ static int __init_cache_level(unsigned int cpu) leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; } + of_level = of_count_cache_levels(cpu); + if (level < of_level) { + /* + * some external caches not specified in CLIDR_EL1 + * the information may be available in the device tree + * only unified external caches are considered here + */ + level = of_level; + leaves += (of_level - level); + } + this_cpu_ci->num_levels = level; this_cpu_ci->num_leaves = leaves; return 0; diff --git i/drivers/of/base.c w/drivers/of/base.c index d4bea3c797d6..8007f3b06cb8 100644 --- i/drivers/of/base.c +++ w/drivers/of/base.c @@ -2267,6 +2267,20 @@ struct device_node *of_find_next_cache_node(const struct device_node *np) return NULL; } +int of_count_cache_levels(unsigned int cpu) +{ + int level = 0; + struct device *cpu_dev = get_cpu_device(cpu); + struct device_node *np = cpu_dev->of_node; + + while (np) { + level++; + np = of_find_next_cache_node(np); + } + + return level; +} + /** * of_graph_parse_endpoint() - parse common endpoint node properties * @node: pointer to endpoint device_node diff --git i/include/linux/of.h w/include/linux/of.h index d72f01009297..c8597ae71ff3 100644 --- i/include/linux/of.h +++ w/include/linux/of.h @@ -280,6 +280,7 @@ extern struct device_node *of_get_child_by_name(const struct device_node *node, /* cache lookup */ extern struct device_node *of_find_next_cache_node(const struct device_node *); +extern int of_count_cache_levels(unsigned int cpu); extern struct device_node *of_find_node_with_property(