From patchwork Mon Dec 23 11:04:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 182379 Delivered-To: patch@linaro.org Received: by 2002:a92:a146:0:0:0:0:0 with SMTP id v67csp276283ili; Mon, 23 Dec 2019 03:05:23 -0800 (PST) X-Google-Smtp-Source: APXvYqykAK/+bDQnnrSjBej9DRBPRJCo6VvfLkPRSsjrBx0f1RS5Svcxj/FpwpPM+CeGf1R2KnED X-Received: by 2002:a9d:478:: with SMTP id 111mr31354016otc.359.1577099123322; Mon, 23 Dec 2019 03:05:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1577099123; cv=none; d=google.com; s=arc-20160816; b=L5HQtpxZpwbeig71ufr6NkRh2Dh9ACIaMus2TKnBst0ltPb478GNXoQ69pEoxA1pFu HPBD0DuzXYkQf5MKsfia7sRuzi/I6UmZVx6EC4o2wequKkkr58WTV1UlUFb5ezrzI0pJ SUlXyTd/xmuci91Q6UhYc3CaBPbTKtfMPPlQqn0ilozIJpydVM153EUvf799ZtW4bP9e SwNlfNdCLGabRvrfT7NOUtkbcmzPuQW+HciWbZb1QDSygNNOx/60lhdhxD3XZCvGXthy T8xJvK1kanQFPYeM/kMJ89uPSbUOTzN8QPOOOGZMyd5EKPmAwYDs0qKAjgucvbJE9/GO zi4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=InxUgyvU8lymSAtilFp+vD1kDqNPZsdnOQIPWDDC2Kc=; b=ljdcLrtwd7ATry11Aa9WeoY06uwWvD5usmaj3DGhN7u+YUCXx8AfNXM10hOS3U9pFw 3yy0eDfZaXjgv5imto2FQSwGqiMG5auwsDYnhDlJlh42yNwqhbbQQTd/FpjAaCHQDWZd eQlyWSEGO5pVyHSM/HJWS82TkwQL8+Z9XdYoCT5AOmWKMcBqamGoXxWAjnO/a75nMyro JoMLgngJ3u7PAsCfLgHgzndLeRSLh6GGQck27NDpuexNiO2wtJNc/5yekHFWsxzNbkB/ F7KJ1QwMmyPywffH6JWVw4rHCIBiQCjSpSDXePdcMGw94jlVjABnbtsCQBhLf70iRnkG Re1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TlhDqKNG; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u25si7492386otg.170.2019.12.23.03.05.23; Mon, 23 Dec 2019 03:05:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TlhDqKNG; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727008AbfLWLFW (ORCPT + 3 others); Mon, 23 Dec 2019 06:05:22 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:44674 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726959AbfLWLFW (ORCPT ); Mon, 23 Dec 2019 06:05:22 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id xBNB5D1n110565; Mon, 23 Dec 2019 05:05:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1577099113; bh=InxUgyvU8lymSAtilFp+vD1kDqNPZsdnOQIPWDDC2Kc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TlhDqKNG0Rfe30Pc+Pl+QdNXGOZ4KB59QZ672eUZ/0cHduxZdL1LwYNpm/jOKL4k0 iKHNfGggrBBhAa/62K/KjyKRuyMrITjdoI4Iy/dmO/nvCuv2VTv0eejD5htHtxjLbY fS9zzumP9UyQ1EroIpqQ1c6tZufCLJgta36o8/VY= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xBNB5D1i106727 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 23 Dec 2019 05:05:13 -0600 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 23 Dec 2019 05:05:04 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 23 Dec 2019 05:05:04 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBNB4eMC025693; Mon, 23 Dec 2019 05:05:00 -0600 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , , , Subject: [PATCH v8 05/18] dmaengine: Add support for reporting DMA cached data amount Date: Mon, 23 Dec 2019 13:04:45 +0200 Message-ID: <20191223110458.30766-6-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20191223110458.30766-1-peter.ujfalusi@ti.com> References: <20191223110458.30766-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org A DMA hardware can have big cache or FIFO and the amount of data sitting in the DMA fabric can be an interest for the clients. For example in audio we want to know the delay in the data flow and in case the DMA have significantly large FIFO/cache, it can affect the latenc/delay Signed-off-by: Peter Ujfalusi Reviewed-by: Tero Kristo Tested-by: Keerthy Reviewed-by: Grygorii Strashko --- drivers/dma/dmaengine.h | 8 ++++++++ include/linux/dmaengine.h | 2 ++ 2 files changed, 10 insertions(+) -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/dma/dmaengine.h b/drivers/dma/dmaengine.h index 501c0b063f85..b0b97475707a 100644 --- a/drivers/dma/dmaengine.h +++ b/drivers/dma/dmaengine.h @@ -77,6 +77,7 @@ static inline enum dma_status dma_cookie_status(struct dma_chan *chan, state->last = complete; state->used = used; state->residue = 0; + state->in_flight_bytes = 0; } return dma_async_is_complete(cookie, complete, used); } @@ -87,6 +88,13 @@ static inline void dma_set_residue(struct dma_tx_state *state, u32 residue) state->residue = residue; } +static inline void dma_set_in_flight_bytes(struct dma_tx_state *state, + u32 in_flight_bytes) +{ + if (state) + state->in_flight_bytes = in_flight_bytes; +} + struct dmaengine_desc_callback { dma_async_tx_callback callback; dma_async_tx_callback_result callback_result; diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 81ce9d2480c4..7f9a7150a632 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -686,11 +686,13 @@ static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descr * @residue: the remaining number of bytes left to transmit * on the selected transfer for states DMA_IN_PROGRESS and * DMA_PAUSED if this is implemented in the driver, else 0 + * @in_flight_bytes: amount of data in bytes cached by the DMA. */ struct dma_tx_state { dma_cookie_t last; dma_cookie_t used; u32 residue; + u32 in_flight_bytes; }; /**