From patchwork Thu Nov 28 10:59:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 180403 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp7356912ilf; Thu, 28 Nov 2019 02:59:59 -0800 (PST) X-Google-Smtp-Source: APXvYqxwqG0XSYEJsIS5QhXyUMWq95+pWCjUHcPNUTSJlObnSTCGLETpmpn2ZlVKamHF9iexVeZM X-Received: by 2002:a05:6402:6c7:: with SMTP id n7mr33881561edy.177.1574938799575; Thu, 28 Nov 2019 02:59:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574938799; cv=none; d=google.com; s=arc-20160816; b=AE6DqHJa0sBmyKCgDJf2Pz6YWlny3tU1snCwq1oK3uutGMXIIKQnnI2MGOEfMlX8ZU aG8SnJerdqwdGCgqQQw+nVIkooDhv8y4B8DY0Mb2buDLnLUDcjR9ULVv39MU1o6Rr//B LIbRyKSTDYV9EZfYzQ9v1Z3f2qk6tv5HSaE28Mr4g/bQgrqeSll4TCKDWeWp4Mn20ja2 47y/3T9cLhWDrMuGFTgUervXLsjkwFtpFwmzd7+cEVPBRaDL+S0YrmvF0pLyOzbu4W4/ kgNK9/8t3D5K27aI11+8YZXfb3L7oznlRL3EVaDfwqqbABaXkWDM+u8H+mA5IXf03cvj oiLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EeH349x8o4SCZvve2w+07qwX2Rkls7hx3AcZBuQt9LU=; b=vTnna85Xpdjm/FyzXSQ0HAOuAQa5zjfpIK1KojUJhIsHugZ2mVZI7NFI/S1JF0uXPN OO7oRuYmU15HKanG/TzlvWOjAWVxcUgHfkSb8muKn4zYbOyc8kCny91oXgc+CWkkGw8m 40RIFjQZj7H0jVFq6XmTr0+7QjAbxknAxKFJMhoFIopX1UcNXNdTitaO+eLcz4seZ3Wp lWZQMuKhEg9ahz7RqSI7t+OEMrt6M9Lf9vPWEQ4UMfYXdY/lJoG1K80AD+xUZ+5fma4C EJ+TOgTnl2VUxxawqfC6XMhyui3/v2F0qw+hhLWbo4jMFUVgxXhg5UUoI72+izxg8Abm aTTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sWhxq+s3; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p11si2167953edm.387.2019.11.28.02.59.59; Thu, 28 Nov 2019 02:59:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sWhxq+s3; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726641AbfK1K76 (ORCPT + 3 others); Thu, 28 Nov 2019 05:59:58 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59160 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726191AbfK1K76 (ORCPT ); Thu, 28 Nov 2019 05:59:58 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xASAxoMf099557; Thu, 28 Nov 2019 04:59:50 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1574938790; bh=EeH349x8o4SCZvve2w+07qwX2Rkls7hx3AcZBuQt9LU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sWhxq+s3W0b+pkKBdLhbIultvfQuGqTfydHKuhZuEGUOEWj33z6YihPboOL6t1dft uAy75xYdY9+wI6iOGGGydQs++Zh+l/S3CHBeQRN3I2Kti7d5/oNx+YvuwgGbM9kguG WoT/XsT1WRF+Bgxp8ZYJZkvH2RWl3mCy5u4HTSCs= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xASAxosP045258 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 28 Nov 2019 04:59:50 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 28 Nov 2019 04:59:49 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 28 Nov 2019 04:59:49 -0600 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xASAxgJF073287; Thu, 28 Nov 2019 04:59:46 -0600 From: Peter Ujfalusi To: , , , CC: , , , , , , , , , Subject: [PATCH v6 01/17] bindings: soc: ti: add documentation for k3 ringacc Date: Thu, 28 Nov 2019 12:59:29 +0200 Message-ID: <20191128105945.13071-2-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191128105945.13071-1-peter.ujfalusi@ti.com> References: <20191128105945.13071-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org From: Grygorii Strashko The Ring Accelerator (RINGACC or RA) provides hardware acceleration to enable straightforward passing of work between a producer and a consumer. There is one RINGACC module per NAVSS on TI AM65x and j721e. This patch introduces RINGACC device tree bindings. Signed-off-by: Grygorii Strashko Signed-off-by: Peter Ujfalusi Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/ti/k3-ringacc.txt | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt -- Peter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt new file mode 100644 index 000000000000..59758ccce809 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt @@ -0,0 +1,59 @@ +* Texas Instruments K3 NavigatorSS Ring Accelerator + +The Ring Accelerator (RA) is a machine which converts read/write accesses +from/to a constant address into corresponding read/write accesses from/to a +circular data structure in memory. The RA eliminates the need for each DMA +controller which needs to access ring elements from having to know the current +state of the ring (base address, current offset). The DMA controller +performs a read or write access to a specific address range (which maps to the +source interface on the RA) and the RA replaces the address for the transaction +with a new address which corresponds to the head or tail element of the ring +(head for reads, tail for writes). + +The Ring Accelerator is a hardware module that is responsible for accelerating +management of the packet queues. The K3 SoCs can have more than one RA instances + +Required properties: +- compatible : Must be "ti,am654-navss-ringacc"; +- reg : Should contain register location and length of the following + named register regions. +- reg-names : should be + "rt" - The RA Ring Real-time Control/Status Registers + "fifos" - The RA Queues Registers + "proxy_gcfg" - The RA Proxy Global Config Registers + "proxy_target" - The RA Proxy Datapath Registers +- ti,num-rings : Number of rings supported by RA +- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range +- ti,sci : phandle on TI-SCI compatible System controller node +- ti,sci-dev-id : TI-SCI device id of the ring accelerator +- msi-parent : phandle for "ti,sci-inta" interrupt controller + +Optional properties: + -- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability + issue software w/a + +Example: + +ringacc: ringacc@3c000000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>; + reg-names = "rt", "fifos", + "proxy_gcfg", "proxy_target"; + ti,num-rings = <818>; + ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ + ti,dma-ring-reset-quirk; + ti,sci = <&dmsc>; + ti,sci-dev-id = <187>; + msi-parent = <&inta_main_udmass>; +}; + +client: + +dma_ipx: dma_ipx@ { + ... + ti,ringacc = <&ringacc>; + ... +}