From patchwork Mon Jan 4 17:48:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 59142 Delivered-To: patch@linaro.org Received: by 10.112.130.2 with SMTP id oa2csp5499004lbb; Mon, 4 Jan 2016 09:50:11 -0800 (PST) X-Received: by 10.98.14.28 with SMTP id w28mr64958738pfi.42.1451929810912; Mon, 04 Jan 2016 09:50:10 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id qz2si59144098pab.53.2016.01.04.09.50.10 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Jan 2016 09:50:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aG9FZ-0005cF-3K; Mon, 04 Jan 2016 17:48:57 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aG9FW-0005bM-6P for linux-arm-kernel@lists.infradead.org; Mon, 04 Jan 2016 17:48:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 740C649; Mon, 4 Jan 2016 09:48:00 -0800 (PST) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C61813F246; Mon, 4 Jan 2016 09:48:31 -0800 (PST) Date: Mon, 4 Jan 2016 17:48:29 +0000 From: Will Deacon To: Dave Martin Subject: Re: [PATCH] arm64: fix relocation of movz instruction with negative immediate Message-ID: <20160104174829.GJ1616@arm.com> References: <1451923762-8387-1-git-send-email-ard.biesheuvel@linaro.org> <20160104171749.GA4436@e103592.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20160104171749.GA4436@e103592.cambridge.arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160104_094854_252923_D942FE08 X-CRM114-Status: GOOD ( 20.75 ) X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Ard Biesheuvel Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org On Mon, Jan 04, 2016 at 05:21:12PM +0000, Dave Martin wrote: > On Mon, Jan 04, 2016 at 05:09:22PM +0100, Ard Biesheuvel wrote: > > The test whether a movz instruction with a signed immediate should be > > turned into a movn instruction (i.e., when the immediate is negative) > > is flawed, since the value of imm is always positive. So check sval > > instead. > > > > Signed-off-by: Ard Biesheuvel > > --- > > arch/arm64/kernel/module.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c > > index f4bc779e62e8..39e4a29cab50 100644 > > --- a/arch/arm64/kernel/module.c > > +++ b/arch/arm64/kernel/module.c > > @@ -128,7 +128,7 @@ static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val, > > #define AARCH64_INSN_IMM_MOVNZ AARCH64_INSN_IMM_MAX > #define AARCH64_INSN_IMM_MOVK AARCH64_INSN_IMM_16 > > /* ... */ > > if (imm_type == AARCH64_INSN_IMM_MOVNZ) { > > /* ... */ > > > * immediate is less than zero. > > */ > > insn &= ~(3 << 29); > > - if ((s64)imm >= 0) { > > + if (sval >= 0) { > > /* >=0: Set the instruction to MOVZ (opcode 10b). */ > > insn |= 2 << 29; > > } else { > > I _think_ this may be correct, but... Yeah, I think this is the right thing to do. > } > imm_type = AARCH64_INSN_IMM_MOVK; > } > > /* Update the instruction with the new encoding. */ > insn = aarch64_insn_encode_immediate(imm_type, insn, imm); > > /* ... */ > > leaves imm_type as either AARCH64_INSN_IMM_16 or AARCH64_INSN_IMM_MOVK. > > But because AARCH64_INSN_IMM_16 == AARCH64_INSN_IMM_MOVK (required for , the negative > overflow fudge is never applied, no? > > if (imm_type != AARCH64_INSN_IMM_16) { > sval++; > limit++; > } Hmm, that's a bug introduced by the refactoring of the insn encoding stuff in c84fced8d990 ("arm64: move encode_insn_immediate() from module.c to insn.c"). I've restored the old behaviour below. > I'm wondering whether there is a less confusing way to do all this... Patches welcome! I didn't have an ELF spec when I wrote the original code, so it might be easier now. It would also be handy to have a test module that uses lots of relocs... Will --->8 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c index 266e7490e85c..6546032bb83b 100644 --- a/arch/arm64/kernel/module.c +++ b/arch/arm64/kernel/module.c @@ -140,11 +140,10 @@ static int reloc_insn_movw(enum aarch64_reloc_op op, void *place, u64 val, */ imm = ~imm; } - imm_type = AARCH64_INSN_IMM_MOVK; } /* Update the instruction with the new encoding. */ - insn = aarch64_insn_encode_immediate(imm_type, insn, imm); + insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm); *(u32 *)place = cpu_to_le32(insn); /* Shift out the immediate field. */