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[2001:1868:205::9]) by mx.google.com with ESMTPS id s32si3561431qgd.93.2014.04.25.02.27.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Apr 2014 02:27:16 -0700 (PDT) Received-SPF: none (google.com: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org does not designate permitted sender hosts) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WdcO9-0002wF-Ft; Fri, 25 Apr 2014 09:25:45 +0000 Received: from fw-tnat.austin.arm.com ([217.140.110.23] helo=collaborate-mta1.arm.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WdcO7-0002tY-C2 for linux-arm-kernel@lists.infradead.org; Fri, 25 Apr 2014 09:25:43 +0000 Received: from arm.com (e102109-lin.cambridge.arm.com [10.1.203.182]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id 2C33113F884; Fri, 25 Apr 2014 04:25:08 -0500 (CDT) Date: Fri, 25 Apr 2014 10:24:37 +0100 From: Catalin Marinas To: Loc Ho Subject: Re: arm64: default dma_ops is set to coherent_dma_ops results into DMA FAILURE Message-ID: <20140425092437.GE13648@arm.com> References: MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140425_022543_455630_9071B695 X-CRM114-Status: GOOD ( 24.46 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.2 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record Cc: Mark Rutland , Will Deacon , "linux-arm-kernel@lists.infradead.org" , "ritesh.harjani@gmail.com" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: catalin.marinas@arm.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Content-Disposition: inline On Fri, Apr 25, 2014 at 06:43:45AM +0100, Loc Ho wrote: > > > This is regarding the default dma_ops that we populate for arm64. > > > > > > PROBLEM: > > > Currently in arch/arm64/mm/dma-mapping.c we set dma_ops = > > > &coherent_swiotlb_dma_ops. > > > > > > The problem with this is, lets say that there is a dma device which > > > has not populated its dev->archdata.dma_ops, then this dma device will > > > get the coherent dma_ops in which we dont do any cache maintainance. > > > > > > So, if the dma driver do kmalloc, make some changes to the buffer and > > > after dma_map_single gives it to the dma for the transfer, due to no > > > cache maintenance performed, result will be DMA transfer failed. > > > > > > > > > > > > Earlier noncoherent ops code was not present at all for arm64, so may > > > be we were setting default ops to coherent ops. But now that we have > > > noncoherent ops in place shall we make the default dma_ops to > > > noncoherent (as what arm also does) ? > > > > The problem with changing the default assumption to non-coherent is that > > existing coherent platforms that rely on the coherent DMA ops being selected > > without any additional DT properties (e.g. dma-coherent) will break with > > this change. > > > > This puts us into a nasty situation where we have the opposite policy from > > arch/arm/ regarding default DMA ops, rendering device-trees potentially > > incompatible between the two architectures. > > > > I'd be inclined to align the two, but it will break any users relying on the > > current behaviour (I believe this includes Applied with their X-gene SoC). > > APM X-Gene SoC SMP system is fully coherent. It is preferred no cache > maintenance operations as it is an over head. Currently, only the SATA > driver is in 3.15-rc2 that is DMA master. If it is switched to > non-coherent, this just adds cache maintenance over head which doesn't > affect the system besides flushing over head. The intention is not to make performance worse for this device but rather add the following to the DT file: Since we don't have any stable release with your driver yet, it makes sense to make such change as soon as possible. diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi index 93f4b2dd9248..f8c40a66e65d 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi @@ -307,6 +307,7 @@ <0x0 0x1f21e000 0x0 0x1000>, <0x0 0x1f217000 0x0 0x1000>; interrupts = <0x0 0x86 0x4>; + dma-coherent; status = "disabled"; clocks = <&sata01clk 0>; phys = <&phy1 0>; @@ -321,6 +322,7 @@ <0x0 0x1f22e000 0x0 0x1000>, <0x0 0x1f227000 0x0 0x1000>; interrupts = <0x0 0x87 0x4>; + dma-coherent; status = "ok"; clocks = <&sata23clk 0>; phys = <&phy2 0>; @@ -334,6 +336,7 @@ <0x0 0x1f23d000 0x0 0x1000>, <0x0 0x1f23e000 0x0 0x1000>; interrupts = <0x0 0x88 0x4>; + dma-coherent; status = "ok"; clocks = <&sata45clk 0>; phys = <&phy3 0>;