From patchwork Wed Apr 2 17:07:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 27650 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f70.google.com (mail-wg0-f70.google.com [74.125.82.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 4190C20341 for ; Wed, 2 Apr 2014 17:08:33 +0000 (UTC) Received: by mail-wg0-f70.google.com with SMTP id k14sf358053wgh.5 for ; Wed, 02 Apr 2014 10:08:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:date:from:to:cc:subject:message-id :references:mime-version:in-reply-to:user-agent:sender:precedence :list-id:x-original-sender:x-original-authentication-results :mailing-list:list-post:list-help:list-archive:list-unsubscribe :content-type:content-disposition; bh=T6S8wHP1U6mxkE84vZfebRiopO9v8POBnsng9c9vmSk=; b=et61jIoGAKV9w3C4MAuG3g7FocSaH2bwh3UA2/YIfqqHnEissmosNsE8mFU7UnEu6W vIeiTERVc28qbdOL24G5Lw9iUJYe2CbJwLnNTFnjpdgroHm0x60rTPEhyDJHXRdSev4w +YFBOWELKzBPszsPnCoCK79KprSYnimIZZV7CWKdka2AaAGM45FgOLnAfKTcwTuHvKKH HfmMOA+kT0UiKqoS7ppKyL5AUjYRMNOVrCZ7TJ5OdiusJ/xq78gypqPw+x21fB4x4Rjy VQMoZV4Hwa9J9ywE/HPiYbu9AtS2nb7rm3lW6mNjrOi1KK4oU/pcVSjhnDTYy90mVrN4 uVUQ== X-Gm-Message-State: ALoCoQmN5JfJuWYoIWw9MHpyLupMurFeOJ4RY31Qmg5fM3dWpPQgsVGxQcCysqKRXRYmRIp0mkvq X-Received: by 10.152.121.100 with SMTP id lj4mr249114lab.5.1396458512173; Wed, 02 Apr 2014 10:08:32 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.41.169 with SMTP id z38ls384997qgz.36.gmail; Wed, 02 Apr 2014 10:08:32 -0700 (PDT) X-Received: by 10.52.78.231 with SMTP id e7mr1826393vdx.28.1396458511984; Wed, 02 Apr 2014 10:08:31 -0700 (PDT) Received: from mail-vc0-f170.google.com (mail-vc0-f170.google.com [209.85.220.170]) by mx.google.com with ESMTPS id tv3si679313vdc.198.2014.04.02.10.08.31 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 02 Apr 2014 10:08:31 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.170; Received: by mail-vc0-f170.google.com with SMTP id hu19so741725vcb.29 for ; Wed, 02 Apr 2014 10:08:31 -0700 (PDT) X-Received: by 10.52.65.165 with SMTP id y5mr1687933vds.51.1396458511840; Wed, 02 Apr 2014 10:08:31 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.12.8 with SMTP id v8csp340314vcv; Wed, 2 Apr 2014 10:08:31 -0700 (PDT) X-Received: by 10.66.232.7 with SMTP id tk7mr1396296pac.94.1396458510726; Wed, 02 Apr 2014 10:08:30 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b5si1622361pbq.104.2014.04.02.10.08.30; Wed, 02 Apr 2014 10:08:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932806AbaDBRIU (ORCPT + 27 others); Wed, 2 Apr 2014 13:08:20 -0400 Received: from fw-tnat.austin.arm.com ([217.140.110.23]:41880 "EHLO collaborate-mta1.arm.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932516AbaDBRIQ (ORCPT ); Wed, 2 Apr 2014 13:08:16 -0400 Received: from arm.com (e102109-lin.cambridge.arm.com [10.1.203.182]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id 1F75113F7CA; Wed, 2 Apr 2014 12:08:10 -0500 (CDT) Date: Wed, 2 Apr 2014 18:07:47 +0100 From: Catalin Marinas To: Joe Sylve Cc: Will Deacon , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30] Message-ID: <20140402170747.GC24018@arm.com> References: <20140402123844.GE31892@arm.com> MIME-Version: 1.0 In-Reply-To: <20140402123844.GE31892@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: catalin.marinas@arm.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Content-Disposition: inline On Wed, Apr 02, 2014 at 01:38:44PM +0100, Catalin Marinas wrote: > On Wed, Apr 02, 2014 at 05:00:38AM +0100, Joe Sylve wrote: > > Section D7.2.83 TCR_EL1, Translation Control Register (EL1) of the > > latest ARM Architecture Reference Manual, ARMv8, for ARMv8-A states > > that TCR_EL1 TG1 (bits [31:30]) should be set to 11 for a 64KB > > TTBR1_EL1 granule size. The mainline 3.14 kernel incorrectly sets > > those bits to 01 (which is a 16KB granule size). > > > > Signed-off-by: Joe Sylve > > --- > > > > --- a/arch/arm64/include/asm/pgtable-hwdef.h 2014-04-01 22:13:22.619868978 -0500 > > +++ b/arch/arm64/include/asm/pgtable-hwdef.h 2014-04-01 22:13:58.071869886 -0500 > > @@ -121,7 +121,7 @@ > > #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) > > #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) > > #define TCR_TG0_64K (UL(1) << 14) > > -#define TCR_TG1_64K (UL(1) << 30) > > +#define TCR_TG1_64K (UL(3) << 30) > > #define TCR_IPS_40BIT (UL(2) << 32) > > #define TCR_ASID16 (UL(1) << 36) > > #define TCR_TBI0 (UL(1) << 37) > > According to the spec, 4K pages is also wrong. The strange thing is that > it works fine on the model. I'll ask internally for clarification > whether it's a typo in the manual or Linux needs fixing. You scared me first but the Linux code is *correct* because it sets bit 31 to 1 in proc.S explicitly. The reason is that the code pre-dates the 16K addition to the spec where bit 31 was RES1 and TG0/TG1 were one bit wide and had the same value. Anyway, it's worth updating the kernel as at some point will add 16K pages support. Something like below: --------8<--------------- >From d43ca2701b5d66ab467ba3f8db52ee02020d38a2 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Wed, 2 Apr 2014 17:55:40 +0100 Subject: [PATCH] arm64: Update the TCR_EL1 translation granule definitions for 16K pages The current TCR register setting in arch/arm64/mm/proc.S assumes that TCR_EL1.TG* fields are one bit wide and bit 31 is RES1 (reserved, set to 1). With the addition of 16K pages (currently unsupported in the kernel), the TCR_EL1.TG* fields have been extended to two bits. This patch updates the corresponding Linux definitions and drops the bit 31 setting in proc.S in favour of the new macros. Signed-off-by: Catalin Marinas Reported-by: Joe Sylve --- arch/arm64/include/asm/pgtable-hwdef.h | 6 +++++- arch/arm64/mm/proc.S | 25 ++++++++++++++----------- 2 files changed, 19 insertions(+), 12 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/ diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index f7af66b54cb2..5fc8a66c3924 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -120,8 +120,12 @@ #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) +#define TCR_TG0_4K (UL(0) << 14) #define TCR_TG0_64K (UL(1) << 14) -#define TCR_TG1_64K (UL(1) << 30) +#define TCR_TG0_16K (UL(2) << 14) +#define TCR_TG1_16K (UL(1) << 30) +#define TCR_TG1_4K (UL(2) << 30) +#define TCR_TG1_64K (UL(3) << 30) #define TCR_ASID16 (UL(1) << 36) #define TCR_TBI0 (UL(1) << 37) diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index e085ee6ef4e2..9042aff5e9e3 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -28,14 +28,21 @@ #include "proc-macros.S" -#ifndef CONFIG_SMP -/* PTWs cacheable, inner/outer WBWA not shareable */ -#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA +#ifdef CONFIG_ARM64_64K_PAGES +#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K +#else +#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K +#endif + +#ifdef CONFIG_SMP +#define TCR_SMP_FLAGS TCR_SHARED #else -/* PTWs cacheable, inner/outer WBWA shareable */ -#define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED +#define TCR_SMP_FLAGS 0 #endif +/* PTWs cacheable, inner/outer WBWA */ +#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA + #define MAIR(attr, mt) ((attr) << ((mt) * 8)) /* @@ -209,18 +216,14 @@ ENTRY(__cpu_setup) * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for * both user and kernel. */ - ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | \ - TCR_ASID16 | TCR_TBI0 | (1 << 31) + ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ + TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 /* * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in * TCR_EL1. */ mrs x9, ID_AA64MMFR0_EL1 bfi x10, x9, #32, #3 -#ifdef CONFIG_ARM64_64K_PAGES - orr x10, x10, TCR_TG0_64K - orr x10, x10, TCR_TG1_64K -#endif msr tcr_el1, x10 ret // return to head.S ENDPROC(__cpu_setup)