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[2001:770:15f::2]) by mx.google.com with ESMTPS id de3si4516228wib.7.2014.03.12.10.35.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 12 Mar 2014 10:35:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:770:15f::2 as permitted sender) client-ip=2001:770:15f::2; Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WNn23-0004mY-TT; Wed, 12 Mar 2014 17:33:32 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WNmwA-0004cb-VE; Wed, 12 Mar 2014 17:27:26 +0000 Received: from fw-tnat.austin.arm.com ([217.140.110.23] helo=collaborate-mta1.arm.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WNmw8-0004b2-5A for linux-arm-kernel@lists.infradead.org; Wed, 12 Mar 2014 17:27:24 +0000 Received: from arm.com (e102109-lin.cambridge.arm.com [10.1.203.182]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id 2DC1113FA7C; Wed, 12 Mar 2014 12:26:59 -0500 (CDT) Date: Wed, 12 Mar 2014 17:26:42 +0000 From: Catalin Marinas To: Will Deacon Subject: Re: [PATCH] ARM64: Kernel managed pages are only flushed Message-ID: <20140312172642.GU17083@arm.com> References: <1394018446-16738-1-git-send-email-Bharat.Bhushan@freescale.com> <20140306065339.GA2975@localhost> <20140312145653.GA9691@mudshark.cambridge.arm.com> <20140312160340.GI17083@arm.com> MIME-Version: 1.0 In-Reply-To: <20140312160340.GI17083@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140312_132724_304991_F394C94B X-CRM114-Status: GOOD ( 20.86 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "Bharat.Bhushan@freescale.com" , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: catalin.marinas@arm.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Content-Disposition: inline On Wed, Mar 12, 2014 at 04:03:40PM +0000, Catalin Marinas wrote: > On Wed, Mar 12, 2014 at 02:56:53PM +0000, Will Deacon wrote: > > On Wed, Mar 12, 2014 at 02:41:31PM +0000, Bharat.Bhushan@freescale.com wrote: > > > Did you get the chance to look into this? What is your take for this patch > > > or you want to suggest some other solution? > > > > See my reply to Laura here: > > > > http://lists.infradead.org/pipermail/linux-arm-kernel/2014-March/238510.html > > > > We *really* don't want executable device mappings. > > /dev/mem mapping use pgprot_noncached() but I think we could generalise > any of the writecombine and dmacoherent mappings to XN like in the patch > below: > > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index b524dcd17243..2d3cede62709 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -286,11 +286,11 @@ static inline int has_transparent_hugepage(void) > * Mark the prot value as uncacheable and unbufferable. > */ > #define pgprot_noncached(prot) \ > - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE)) > + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) > #define pgprot_writecombine(prot) \ > - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)) > + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) > #define pgprot_dmacoherent(prot) \ > - __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)) > + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) > #define __HAVE_PHYS_MEM_ACCESS_PROT > struct file; > extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, And one more patch as suggested by Steve Capper. Both would be needed. -------------8<---------------------- >From 31d84855d71778e4a0f615f61ab836be3a70a58b Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Wed, 12 Mar 2014 16:28:09 +0000 Subject: [PATCH] arm64: Do not synchronise I and D caches for special ptes Special pte mappings are not intended to be executable and do not even have an associated struct page. This patch ensures that we do not call __sync_icache_dcache() on such ptes. Signed-off-by: Catalin Marinas Reported-by: Steve Capper Tested-by: Bharat Bhushan --- arch/arm64/include/asm/pgtable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 2d3cede62709..72c9ac38cdd9 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -199,7 +199,7 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte) { if (pte_valid_user(pte)) { - if (pte_exec(pte)) + if (!pte_special(pte) && pte_exec(pte)) __sync_icache_dcache(pte, addr); if (pte_dirty(pte) && pte_write(pte)) pte_val(pte) &= ~PTE_RDONLY;