From patchwork Tue Mar 15 19:56:03 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Green X-Patchwork-Id: 589 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:44:01 -0000 Delivered-To: patches@linaro.org Received: by 10.151.46.5 with SMTP id y5cs80482ybj; Tue, 15 Mar 2011 12:56:08 -0700 (PDT) Received: by 10.216.183.148 with SMTP id q20mr12202735wem.88.1300218967745; Tue, 15 Mar 2011 12:56:07 -0700 (PDT) Received: from mail-ww0-f42.google.com (mail-ww0-f42.google.com [74.125.82.42]) by mx.google.com with ESMTPS id m53si300507wej.87.2011.03.15.12.56.05 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 15 Mar 2011 12:56:06 -0700 (PDT) Received-SPF: pass (google.com: domain of andy.warmcat.com@googlemail.com designates 74.125.82.42 as permitted sender) client-ip=74.125.82.42; Authentication-Results: mx.google.com; spf=pass (google.com: domain of andy.warmcat.com@googlemail.com designates 74.125.82.42 as permitted sender) smtp.mail=andy.warmcat.com@googlemail.com; dkim=pass (test mode) header.i=@googlemail.com Received: by wwk4 with SMTP id 4so3297987wwk.1 for ; Tue, 15 Mar 2011 12:56:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:sender:from:subject:to:cc:date:message-id :in-reply-to:references:user-agent:mime-version:content-type :content-transfer-encoding; bh=WHdTIySwPqc75DnPyLFmTpLKflKbCt9U02eeCITVZMI=; b=jp8WnuGRiSIfmiJUXmlZb0cgUdYNCeZ97460aUWlhZpJPeu7CMqSulbK4Adduudq7I gYa1Lt3XwQhpni+va9DlnebxmkEXd32qij9XG9vL0NsuLIo4/42LIsTOxWwkSvaF/F4/ mzBnguWSqF3UX6hSFt4sQE5dI5vBCxVRas0j0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=sender:from:subject:to:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; b=iWaekuz/LJROi3GhphFj3Y2EjYKDyfn1gNTXCVWiNn0t3CWaQhafpDwivGwaHhr9M/ JkIVYwAn8weqQUhEg3y7KwYgTja2HQjrC2KSRQtslI6y8XbTTBsYX4+YNnjRPe7fwxgF /KtNrmRTPTo/n5xvjfQTdAD2uo1olTg2emwgU= Received: by 10.216.221.16 with SMTP id q16mr12205971wep.71.1300218965616; Tue, 15 Mar 2011 12:56:05 -0700 (PDT) Received: from otae.warmcat.com (s15404224.onlinehome-server.info [87.106.134.80]) by mx.google.com with ESMTPS id n4sm111437wee.4.2011.03.15.12.56.04 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 15 Mar 2011 12:56:05 -0700 (PDT) Sender: Andy Green From: Andy Green Subject: [PATCH 3 02/18] I2C: OMAP2+: Name registers in I2C IP V2 only accordingly To: linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org Cc: patches@linaro.org, Ben Dooks , Andy Green Date: Tue, 15 Mar 2011 19:56:03 +0000 Message-ID: <20110315195602.30000.79880.stgit@otae.warmcat.com> In-Reply-To: <20110315195147.30000.86184.stgit@otae.warmcat.com> References: <20110315195147.30000.86184.stgit@otae.warmcat.com> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 The OMAP I2C driver dynamically chooses between two register sets of differing sizes depending on the cpu type it finds itself on. It has been observed that the existing code references non-existing registers on OMAP3530, because while it correctly chose the smaller register layout based on cpu type, the code uses the probed register ID to decide if to execute code referencing an extra register, and both register layout devices on OMAP3530 and OMAP4430 report the same probed ID of 0x40. This patch changes the extended register names only found on IP V2 of the I2C peripheral unit accordingly to help show up errors in usage. Cc: patches@linaro.org Cc: Ben Dooks Reported-by: Peter Maydell Signed-off-by: Andy Green --- drivers/i2c/busses/i2c-omap.c | 23 ++++++++++++----------- 1 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 829a2a1..2826c13 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -72,11 +72,12 @@ enum { OMAP_I2C_SCLH_REG, OMAP_I2C_SYSTEST_REG, OMAP_I2C_BUFSTAT_REG, - OMAP_I2C_REVNB_LO, - OMAP_I2C_REVNB_HI, - OMAP_I2C_IRQSTATUS_RAW, - OMAP_I2C_IRQENABLE_SET, - OMAP_I2C_IRQENABLE_CLR, + /* only on OMAP4430 */ + OMAP_I2C_IP_V2_REVNB_LO, + OMAP_I2C_IP_V2_REVNB_HI, + OMAP_I2C_IP_V2_IRQSTATUS_RAW, + OMAP_I2C_IP_V2_IRQENABLE_SET, + OMAP_I2C_IP_V2_IRQENABLE_CLR, }; /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ @@ -244,11 +245,11 @@ const static u8 omap4_reg_map[] = { [OMAP_I2C_SCLH_REG] = 0xb8, [OMAP_I2C_SYSTEST_REG] = 0xbC, [OMAP_I2C_BUFSTAT_REG] = 0xc0, - [OMAP_I2C_REVNB_LO] = 0x00, - [OMAP_I2C_REVNB_HI] = 0x04, - [OMAP_I2C_IRQSTATUS_RAW] = 0x24, - [OMAP_I2C_IRQENABLE_SET] = 0x2c, - [OMAP_I2C_IRQENABLE_CLR] = 0x30, + [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, + [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, + [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, + [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, + [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, }; static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, @@ -309,7 +310,7 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev) dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); if (dev->rev >= OMAP_I2C_REV_ON_4430) - omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1); + omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1); else omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);