From patchwork Thu Mar 3 13:50:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Green X-Patchwork-Id: 297 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:41:32 -0000 Delivered-To: patches@linaro.org Received: by 10.224.19.208 with SMTP id c16cs243598qab; Thu, 3 Mar 2011 05:50:41 -0800 (PST) Received: by 10.227.127.65 with SMTP id f1mr910653wbs.209.1299160240483; Thu, 03 Mar 2011 05:50:40 -0800 (PST) Received: from mail-wy0-f178.google.com (mail-wy0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id j7si2106667wbc.19.2011.03.03.05.50.39 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 03 Mar 2011 05:50:40 -0800 (PST) Received-SPF: pass (google.com: domain of andy.warmcat.com@googlemail.com designates 74.125.82.178 as permitted sender) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=pass (google.com: domain of andy.warmcat.com@googlemail.com designates 74.125.82.178 as permitted sender) smtp.mail=andy.warmcat.com@googlemail.com; dkim=pass (test mode) header.i=@googlemail.com Received: by mail-wy0-f178.google.com with SMTP id 28so1247412wyf.37 for ; Thu, 03 Mar 2011 05:50:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:sender:from:subject:to:cc:date:message-id :in-reply-to:references:user-agent:mime-version:content-type :content-transfer-encoding; bh=yxL0qBem0f+p2qRBgA3hP/auATUVRDVDuorGpIyEl/I=; b=Yj0alHw1lwAr2Rtn/Yo2bVf3qWnFrFWrAZ1dLMfdy/UwmFODCMfW15k3gh1Y5v9+To K6nbje6v8TGhbEPXO9/SrNSyB6zOWAdnjofQPWLDeLiVvIWYaReVG2uBjlZSGzNLMIZw bd6cH8vIcKXyUT41ZlGY41E3sEvg7D2VnMXlg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=sender:from:subject:to:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; b=Ar72a/UTpJMynO5DeoYwlHFriVzQtdJ0PlY8Nl2PjTIznLL4ZOAChta1xl8nF/+G+I aVH5X+Pg+7WPMhuqG+IhbUyPzD2QhyktfYwD73fSS/0n2bvm3MmAj2tBLjWvLgdERr9D 9/hVIyBWcC/xLg1HWePatnVVvi2wd5q2b+6ss= Received: by 10.216.180.76 with SMTP id i54mr676786wem.33.1299160239583; Thu, 03 Mar 2011 05:50:39 -0800 (PST) Received: from otae.warmcat.com (s15404224.onlinehome-server.info [87.106.134.80]) by mx.google.com with ESMTPS id r6sm326445weq.20.2011.03.03.05.50.38 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 03 Mar 2011 05:50:39 -0800 (PST) Sender: Andy Green From: Andy Green Subject: [PATCH 3/4] OMAP3 and 4 i2c mark extended reg enums as extended only To: linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org Cc: patches@linaro.org, Andy Green Date: Thu, 03 Mar 2011 13:50:37 +0000 Message-ID: <20110303135037.30648.90406.stgit@otae.warmcat.com> In-Reply-To: <20110303134744.30648.91218.stgit@otae.warmcat.com> References: <20110303134744.30648.91218.stgit@otae.warmcat.com> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 The OMAP I2C driver dynamically chooses between two register sets of differing sizes depending on the cpu type it finds itself on. It has been observed that the existing code references non-existing registers on OMAP3530, because while it correctly chose the smaller register layout based on cpu type, the code uses the probed register ID to decide if to execute code referencing an extra register, and both register layout devices on OMAP3530 and OMAP4430 report the same probed ID of 0x40. This patch changes the extended register name to make it clearer they only exist in OMAP4 context Cc: patches@linaro.org Reported-by: Peter Maydell Signed-off-by: Andy Green --- drivers/i2c/busses/i2c-omap.c | 23 ++++++++++++----------- 1 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index d6500ec..e09c62d 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -72,11 +72,12 @@ enum { OMAP_I2C_SCLH_REG, OMAP_I2C_SYSTEST_REG, OMAP_I2C_BUFSTAT_REG, - OMAP_I2C_REVNB_LO, - OMAP_I2C_REVNB_HI, - OMAP_I2C_IRQSTATUS_RAW, - OMAP_I2C_IRQENABLE_SET, - OMAP_I2C_IRQENABLE_CLR, + /* only on OMAP4430 */ + OMAP_I2C_OMAP4430_REVNB_LO, + OMAP_I2C_OMAP4430_REVNB_HI, + OMAP_I2C_OMAP4430_IRQSTATUS_RAW, + OMAP_I2C_OMAP4430_IRQENABLE_SET, + OMAP_I2C_OMAP4430_IRQENABLE_CLR, }; /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ @@ -244,11 +245,11 @@ const static u8 omap4_reg_map[] = { [OMAP_I2C_SCLH_REG] = 0xb8, [OMAP_I2C_SYSTEST_REG] = 0xbC, [OMAP_I2C_BUFSTAT_REG] = 0xc0, - [OMAP_I2C_REVNB_LO] = 0x00, - [OMAP_I2C_REVNB_HI] = 0x04, - [OMAP_I2C_IRQSTATUS_RAW] = 0x24, - [OMAP_I2C_IRQENABLE_SET] = 0x2c, - [OMAP_I2C_IRQENABLE_CLR] = 0x30, + [OMAP_I2C_OMAP4430_REVNB_LO] = 0x00, + [OMAP_I2C_OMAP4430_REVNB_HI] = 0x04, + [OMAP_I2C_OMAP4430_IRQSTATUS_RAW] = 0x24, + [OMAP_I2C_OMAP4430_IRQENABLE_SET] = 0x2c, + [OMAP_I2C_OMAP4430_IRQENABLE_CLR] = 0x30, }; static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, @@ -309,7 +310,7 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev) dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); if (dev->rev >= OMAP_I2C_REV_ON_4430) - omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1); + omap_i2c_write_reg(dev, OMAP_I2C_OMAP4430_IRQENABLE_CLR, 1); else omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);