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[65.50.211.133]) by mx.google.com with ESMTPS id 62si7293966ply.77.2017.01.28.05.29.15 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 28 Jan 2017 05:29:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 65.50.211.133 as permitted sender) client-ip=65.50.211.133; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 65.50.211.133 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cXT45-00026k-HW; Sat, 28 Jan 2017 13:29:13 +0000 Received: from conuserg-12.nifty.com ([210.131.2.79]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cXT3B-0001tu-7r for linux-arm-kernel@lists.infradead.org; Sat, 28 Jan 2017 13:28:20 +0000 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-12.nifty.com with ESMTP id v0SDR4sx002858; Sat, 28 Jan 2017 22:27:08 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com v0SDR4sx002858 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1485610028; bh=+nowblP6G5tr3CgHPBhFwInUPouwmGprWEBJPyllYyo=; h=From:To:Cc:Subject:Date:From; b=ijuCZKAt1v+hijQCqm+ibdlQAOLkH4VMuBSPhCwka7VxdXVAkt9Lhbq20Oou8QrJ/ sZfdGQ5HnSMZ3gg5Nr4sR+htQogBP+5U26FG/zqpByM/4Ik43+vDH9atJetHfq18RW ZFRZz+ePRoAC8W9DW+qwB56S1KdmOQBvLeY4i6K7/P05mW26TmxltAHLm8mS2uRxD3 NOVPGT7P4vYcQbrOho5SBA0h68l4Fw/OuezHoeBw/G6Q76JwLSlm1fFe+d5kT8E5JT r9rTEqlQwgXfyHaGZzhtHCoszYcpzYNZVQb6x6Sq4cmKOH6uRtjcd04XDaqh1ZRCPF 1J2eZU2rMoxpw== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-clk@vger.kernel.org Subject: [PATCH 1/2] clk: uniphier: add NAND clock for all UniPhier SoCs Date: Sat, 28 Jan 2017 22:27:00 +0900 Message-Id: <1485610021-9905-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170128_052817_643255_C9683BCF X-CRM114-Status: UNSURE ( 6.51 ) X-CRM114-Notice: Please train this message. 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Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/clk-uniphier-sys.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index d049316..b1aaf77 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -29,6 +29,12 @@ UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \ UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15) +#define UNIPHIER_SLD3_SYS_CLK_NAND(idx) \ + UNIPHIER_CLK_GATE("nand", (idx), NULL, 0x2104, 2) + +#define UNIPHIER_LD11_SYS_CLK_NAND(idx) \ + UNIPHIER_CLK_GATE("nand", (idx), NULL, 0x210c, 0) + #define UNIPHIER_SLD3_SYS_CLK_STDMAC(idx) \ UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10) @@ -48,6 +54,7 @@ const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), + UNIPHIER_SLD3_SYS_CLK_NAND(2), UNIPHIER_SLD3_SYS_CLK_SD, UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), UNIPHIER_SLD3_SYS_CLK_STDMAC(8), @@ -61,6 +68,7 @@ const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), + UNIPHIER_SLD3_SYS_CLK_NAND(2), UNIPHIER_SLD3_SYS_CLK_SD, UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ @@ -74,6 +82,7 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32), + UNIPHIER_SLD3_SYS_CLK_NAND(2), UNIPHIER_SLD3_SYS_CLK_SD, UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */ @@ -89,6 +98,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16), + UNIPHIER_SLD3_SYS_CLK_NAND(2), UNIPHIER_SLD3_SYS_CLK_SD, UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */ @@ -101,6 +111,7 @@ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), + UNIPHIER_SLD3_SYS_CLK_NAND(2), UNIPHIER_PRO5_SYS_CLK_SD, UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC */ UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */ @@ -113,6 +124,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), + UNIPHIER_SLD3_SYS_CLK_NAND(2), UNIPHIER_PRO5_SYS_CLK_SD, UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, RLE */ /* GIO is always clock-enabled: no function for 0x2104 bit6 */ @@ -131,6 +143,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), + UNIPHIER_LD11_SYS_CLK_NAND(2), UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */ UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25), /* CPU gears */ @@ -156,6 +169,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40), + UNIPHIER_LD11_SYS_CLK_NAND(2), UNIPHIER_LD20_SYS_CLK_SD, UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */ /* GIO is always clock-enabled: no function for 0x210c bit5 */