From patchwork Wed Oct 19 12:39:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 78240 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp227774qge; Wed, 19 Oct 2016 05:41:55 -0700 (PDT) X-Received: by 10.99.140.12 with SMTP id m12mr8996745pgd.45.1476880915054; Wed, 19 Oct 2016 05:41:55 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id i7si40354345pfe.46.2016.10.19.05.41.54 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Oct 2016 05:41:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bwq9F-00084A-SB; Wed, 19 Oct 2016 12:39:09 +0000 Received: from conuserg-10.nifty.com ([210.131.2.77]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bwq9A-0007wW-Mo for linux-arm-kernel@lists.infradead.org; Wed, 19 Oct 2016 12:39:06 +0000 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id u9JCbuMO021687; Wed, 19 Oct 2016 21:37:57 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com u9JCbuMO021687 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1476880677; bh=wh8a7VIMUwYGQDAi+6zqoj4EWoYVo78JtZd6QmqEl40=; h=From:To:Cc:Subject:Date:From; b=CM6eC5jbpgcmWyymfd2G6SxLGG/5el051MvHcFZ5bCkrklYl3tnY24vSrNvOyfqqJ GJUx4t0NMguB34pFgMdE2s5+SCjN5lJLdgxtmWRot/9sNmbjUIMNE6tcHD07sRXDPQ wWLqcnkxVrtqvMJ0b/lNUtVk8kh/D3v96Y/ahBPYssnbTDkMS1LWlVw+Mcj0BZ7waO Jo3rvnI2OMWYrvhvhm5B8t19pu62WBoeALEZWkSRrQ8aplvrsdMJIHRuXKsrVQT50X dXbKbQggN+pbjdFWrC/GyfeWOdQfpmCnKFMsYj40NG9xfMSfXVCSZuTuOuMJfZEIYw 0kTrFiKv6rcTg== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: mm: add ARM_L1_CACHE_SHIFT_7 for UniPhier outer cache Date: Wed, 19 Oct 2016 21:39:37 +0900 Message-Id: <1476880777-5068-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161019_053905_056215_30820228 X-CRM114-Status: GOOD ( 11.52 ) X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Jonathan Austin , Arnd Bergmann , Linus Walleij , linux-kernel@vger.kernel.org, Russell King , Masahiro Yamada , Zhaoxiu Zeng , Kees Cook MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The UniPhier outer cache (arch/arm/mm/cache-uniphier.c) has 128 byte line length and its tags are also managed per 128 byte line. This is very unfortunate, but the current 64 byte alignment for kmalloc() causes sharing problems on DMA if used with this outer cache. This commit adds ARM_L1_CACHE_SHIFT_7 to increase the DMA minimum alignment to 128 byte if CACHE_UNIPHIER is enabled. There are several drivers that assume aligning to L1_CACHE_BYTES will be DMA safe, so this commit also changes the L1_CACHE_BYTES for safety. Having said that, I hesitate to align all the other SoCs in Multi platform to the UniPhier's requirement. So, I am disabling the CONFIG_CACHE_UNIPHIER by default, so that multi_v7_defconfig will still with CONFIG_ARM_L1_CACHE_SHIFT=6. With this, UniPhier SoCs become a bit slower, but it is much better than system crash. If desired, the outer-cache can be enabled by the merge_config or something. Note: The UniPhier PH1-Pro5 SoC is equipped also with L3 cache with 256 byte line size but its tags are managed per 128 byte sub-line. So, ARM_L1_CACHE_SHIFT_7 should be fine for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada --- I threw a question in January this year: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/400289.html After a long interval, I came back to this topic. arch/arm/mm/Kconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index c1799dd..f68e8ec 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -991,7 +991,7 @@ config CACHE_TAUROS2 config CACHE_UNIPHIER bool "Enable the UniPhier outer cache controller" depends on ARCH_UNIPHIER - default y + select ARM_L1_CACHE_SHIFT_7 select OUTER_CACHE select OUTER_CACHE_SYNC help @@ -1012,8 +1012,14 @@ config ARM_L1_CACHE_SHIFT_6 help Setting ARM L1 cache line size to 64 Bytes. +config ARM_L1_CACHE_SHIFT_7 + bool + help + Setting ARM L1 cache line size to 128 Bytes. + config ARM_L1_CACHE_SHIFT int + default 7 if ARM_L1_CACHE_SHIFT_7 default 6 if ARM_L1_CACHE_SHIFT_6 default 5