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[2001:1868:205::9]) by mx.google.com with ESMTPS id a189si50440687pfa.80.2016.08.31.04.07.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Aug 2016 04:07:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bf3M0-0000Nq-3b; Wed, 31 Aug 2016 11:06:48 +0000 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bf3LA-0008FS-T1 for linux-arm-kernel@lists.infradead.org; Wed, 31 Aug 2016 11:05:59 +0000 Received: by mail-wm0-x22c.google.com with SMTP id i5so82838158wmg.0 for ; Wed, 31 Aug 2016 04:05:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oxNxZpCxMbPoA2vY8Ys5mdzpC5oOcQT9GJOFeLJOyt0=; b=Ada4eEcvwb2IZyfKYDn0oYiaPsQtXQ4oADfQPK8EagRY5ukpEwyxxUAyKabMNknqZC kX1bgEtwGfR+EA6VK4gn10UKDJUz7BNMTYRFVQFWdM7zHfkwky+Vp0Cb6YgtuW+9AhFo f821ffYZ/5Bn1ASBBLplOG+JkDi/UtG6ZBIiU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oxNxZpCxMbPoA2vY8Ys5mdzpC5oOcQT9GJOFeLJOyt0=; b=mL0PATCJHpQNldI/fO6qyQYtnvYuLK/kJD7RxygJvFbLn7tYIGs4mzWhLmSys4G0hw 45i7w2b3OtqMTRaFUYkZmMP0uv9l7zW3O9apMD2tWvardWdYAKB09gB7jAgq3squx9zs umvOfAUYvuSSpGEvk2Vjy+/yJsr8/cGCbBw7KJZ8Q2JKKWrWcmtP9LkNjo+Gqfpz5jyB h83fS68wlir3H2TAJTMTYKjT+vfo268QwVdTJLsJVA/Z8qWgsvLl9gyhqFoySgdKYJDQ k21yITyRQYjZ9MaH5/wv6iOOGEX6ArEj6RtP0oZyvcrYMJ7ltnHtPHrX8tW/ZAcUFBUr RiqQ== X-Gm-Message-State: AE9vXwNTWgZc6ASKrzZLcwtleIi46yZWwgovBbh45HanwzYGKZ1jaGUx9f49af1Yt3g+d9mq X-Received: by 10.28.145.20 with SMTP id t20mr9382677wmd.74.1472641534739; Wed, 31 Aug 2016 04:05:34 -0700 (PDT) Received: from localhost.localdomain ([160.169.158.74]) by smtp.gmail.com with ESMTPSA id jq5sm44052154wjc.20.2016.08.31.04.05.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Aug 2016 04:05:34 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, will.deacon@arm.com Subject: [PATCH v3 4/7] arm64: kernel: use x30 for __enable_mmu return address Date: Wed, 31 Aug 2016 12:05:14 +0100 Message-Id: <1472641517-15362-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472641517-15362-1-git-send-email-ard.biesheuvel@linaro.org> References: <1472641517-15362-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160831_040557_273815_2D1B8F78 X-CRM114-Status: GOOD ( 13.26 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:400c:c09:0:0:0:22c listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, catalin.marinas@arm.com, Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Using x27 for passing to __enable_mmu what is essentially the return address makes the code look more complicated than it needs to be. So switch to x30/lr, and update the secondary and cpu_resume call sites to simply call __enable_mmu as an ordinary function, with a bl instruction. This requires the callers to be covered by .idmap.text. Reviewed-by: Mark Rutland Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 21 +++++++------------- arch/arm64/kernel/sleep.S | 8 ++------ 2 files changed, 9 insertions(+), 20 deletions(-) -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 5543068da3ae..45b865e022cc 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -675,9 +675,9 @@ secondary_startup: * Common entry point for secondary CPUs. */ bl __cpu_setup // initialise processor - - adr_l x27, __secondary_switch // address to jump to after enabling the MMU - b __enable_mmu + bl __enable_mmu + ldr x8, =__secondary_switched + br x8 ENDPROC(secondary_startup) __secondary_switched: @@ -716,9 +716,9 @@ ENDPROC(__secondary_switched) * Enable the MMU. * * x0 = SCTLR_EL1 value for turning on the MMU. - * x27 = *virtual* address to jump to upon completion * - * Other registers depend on the function called upon completion. + * Returns to the caller via x30/lr. This requires the caller to be covered + * by the .idmap.text section. * * Checks if the selected granule size is supported by the CPU. * If it isn't, park the CPU @@ -744,7 +744,7 @@ ENTRY(__enable_mmu) ic iallu dsb nsh isb - br x27 + ret ENDPROC(__enable_mmu) __no_granule_support: @@ -789,9 +789,7 @@ __primary_switch: mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value #endif - adr x27, 0f - b __enable_mmu -0: + bl __enable_mmu #ifdef CONFIG_RELOCATABLE bl __relocate_kernel #ifdef CONFIG_RANDOMIZE_BASE @@ -822,8 +820,3 @@ __primary_switch: ldr x8, =__primary_switched br x8 ENDPROC(__primary_switch) - -__secondary_switch: - ldr x8, =__secondary_switched - br x8 -ENDPROC(__secondary_switch) diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S index 6adc76bf8f91..0f7e0b2ac64c 100644 --- a/arch/arm64/kernel/sleep.S +++ b/arch/arm64/kernel/sleep.S @@ -100,14 +100,10 @@ ENTRY(cpu_resume) bl el2_setup // if in EL2 drop to EL1 cleanly bl __cpu_setup /* enable the MMU early - so we can access sleep_save_stash by va */ - adr_l x27, _resume_switched /* __enable_mmu will branch here */ - b __enable_mmu -ENDPROC(cpu_resume) - -_resume_switched: + bl __enable_mmu ldr x8, =_cpu_resume br x8 -ENDPROC(_resume_switched) +ENDPROC(cpu_resume) .ltorg .popsection