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[2001:1868:205::9]) by mx.google.com with ESMTPS id j80si50472892pfa.194.2016.08.31.04.10.14 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 31 Aug 2016 04:10:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bf3OC-0001oh-07; Wed, 31 Aug 2016 11:09:04 +0000 Received: from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bf3L6-00089y-68 for linux-arm-kernel@lists.infradead.org; Wed, 31 Aug 2016 11:05:54 +0000 Received: by mail-wm0-x22f.google.com with SMTP id 1so33873969wmz.1 for ; Wed, 31 Aug 2016 04:05:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2QAnOe2DY/Lit5BNh7A6FoZa4en/VyVy5IxpyzTqmLI=; b=BdyW+9lfSqFughHOPt5A3dRWq9Q8dD0L1nM0j3nHCvwVkShg4jvtg7j+hImGuyT778 doN05PZh6dFZmmQqvaMg46kRMTxIOYFlqQl6OVzsTvrr+FvBHM0sgUkJOBkCDONlXOkx tPg7T3d6QBOORZ63msXT31x1sCg8S7obuEPqU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2QAnOe2DY/Lit5BNh7A6FoZa4en/VyVy5IxpyzTqmLI=; b=RLSm6cI9wABCMTiB/qP1Y2EDsaYDCExynwv/CvfeVH/rtlj6r6ZSJuiqnbRq6QfohN YM7a1biSeQlfhxZM1wI5TPt+DO3oTLyQZZynkXotDHUwnFM3R0CEvovrHSj/jktJCoJs 2SSeA1JnByMo+pS9AvGZQicWalpie3bJ4IlWeGS7Fyxw8ykq2lvg8t3Oz5X6SCxpLz2n 8aIacm8CULhmGvazNiwQdhA/UIUQ/BIycm+NtXsaWvgO+cToKHH58OHRdWgR55MYu3mm 23XmL/EllMaiKf5wAp4++8/e01DrV79W8t6k2vCQr7R5jzKE29UWh0Zf+y97UsKj4nGy Q53Q== X-Gm-Message-State: AE9vXwMyvB257aKL48aRe44O14WpoLbjPbhOvgje05nK6nSgIaTRyMcQf24BgdDNi1ypFOKT X-Received: by 10.194.37.101 with SMTP id x5mr9549495wjj.95.1472641530162; Wed, 31 Aug 2016 04:05:30 -0700 (PDT) Received: from localhost.localdomain ([160.169.158.74]) by smtp.gmail.com with ESMTPSA id jq5sm44052154wjc.20.2016.08.31.04.05.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Aug 2016 04:05:29 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, will.deacon@arm.com Subject: [PATCH v3 2/7] arm64: kernel: use ordinary return/argument register for el2_setup() Date: Wed, 31 Aug 2016 12:05:12 +0100 Message-Id: <1472641517-15362-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472641517-15362-1-git-send-email-ard.biesheuvel@linaro.org> References: <1472641517-15362-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160831_040552_511841_2D7D9435 X-CRM114-Status: GOOD ( 11.26 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:400c:c09:0:0:0:22f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, catalin.marinas@arm.com, Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The function el2_setup() passes its return value in register w20, and in the two cases where the caller actually cares about this return value, it is passed into set_cpu_boot_mode_flag() [almost] directly, which expects its input in w20 as well. So there is no reason to use a 'special' callee saved register here, but we can simply follow the PCS for return value and first argument, respectively. Reviewed-by: Mark Rutland Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 024812bfce34..647aa82f2c7b 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -210,7 +210,7 @@ efi_header_end: ENTRY(stext) bl preserve_boot_args - bl el2_setup // Drop to EL1, w20=cpu_boot_mode + bl el2_setup // Drop to EL1, w0=cpu_boot_mode adrp x24, __PHYS_OFFSET and x23, x24, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 bl set_cpu_boot_mode_flag @@ -488,7 +488,7 @@ CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 msr sctlr_el1, x0 - mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 + mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 isb ret @@ -584,7 +584,7 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems cbz x2, install_el2_stub - mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 + mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 isb ret @@ -599,7 +599,7 @@ install_el2_stub: PSR_MODE_EL1h) msr spsr_el2, x0 msr elr_el2, lr - mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 + mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 eret ENDPROC(el2_setup) @@ -609,10 +609,10 @@ ENDPROC(el2_setup) */ set_cpu_boot_mode_flag: adr_l x1, __boot_cpu_mode - cmp w20, #BOOT_CPU_MODE_EL2 + cmp w0, #BOOT_CPU_MODE_EL2 b.ne 1f add x1, x1, #4 -1: str w20, [x1] // This CPU has booted in EL1 +1: str w0, [x1] // This CPU has booted in EL1 dmb sy dc ivac, x1 // Invalidate potentially stale cache line ret @@ -649,7 +649,7 @@ ENTRY(__early_cpu_boot_status) * cores are held until we're ready for them to initialise. */ ENTRY(secondary_holding_pen) - bl el2_setup // Drop to EL1, w20=cpu_boot_mode + bl el2_setup // Drop to EL1, w0=cpu_boot_mode bl set_cpu_boot_mode_flag mrs x0, mpidr_el1 mov_q x1, MPIDR_HWID_BITMASK