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[2001:1868:205::9]) by mx.google.com with ESMTPS id n206si14491734oib.39.2016.08.26.07.34.55 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Aug 2016 07:34:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bdICX-0005fw-39; Fri, 26 Aug 2016 14:33:45 +0000 Received: from mail-pa0-x22d.google.com ([2607:f8b0:400e:c03::22d]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bdIC9-0005Ww-Iu for linux-arm-kernel@lists.infradead.org; Fri, 26 Aug 2016 14:33:25 +0000 Received: by mail-pa0-x22d.google.com with SMTP id fi15so27870162pac.1 for ; Fri, 26 Aug 2016 07:33:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SRBc9jWkwfHAB1ptoBptCmtOgqgJpnQ1yRINNQPDOUA=; b=MMuc1SuLyuayFgWfv1OloxzlC1dJqvjBsnMb9S6USGRoAJOg+f2Xrt2KixHCS6965m e67gnQGAccntk+H7fh+FwHLEnp/SdjeDmlJ5jumjJkmq9shFySWaz0o+EgSiDebCfNiS Mbdsbvzyjak+yiAsS6V4qXtJzesN6JuNGxgYQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SRBc9jWkwfHAB1ptoBptCmtOgqgJpnQ1yRINNQPDOUA=; b=h1dvuMKzGw2Q9ET1uS2TL7GpWsCzVWGkdqVy6ApmMqWJxMWF6qIudxKrf3OW6A624i sD8709uHnqFxWuk8aZygk7xfnm9ijNZgOuqD3hBFSIVoN2RRZ4ih4AvGDR+3b0DyIl5B eUdTFBGpfBrMrZhfDRNKqp5VHPSojt/hrml9rvjYOOjzlrhtTG9XWVpJGC7NkjcQ9Kwy RNxMMjSDp9UogKbzIxNDSZQC8RstRQfEEiuRNIo4IMSsDHKEMM7AYORA1zVjYIvYpnhc DqYGdURcc46Lnv85SLxcZL0SZ/8gESsqDuBZf5AjnAh7lTfojk5p6Ix2pT8WnRj0F6Vw h9lg== X-Gm-Message-State: AE9vXwMX33EAwT1Lz0bZ8I0vYKO2BNfVLUQeoR8p65pqu/sgMzQBuVhnJIzRRCq1rWLU4ujQ X-Received: by 10.66.76.132 with SMTP id k4mr6653813paw.22.1472221980263; Fri, 26 Aug 2016 07:33:00 -0700 (PDT) Received: from localhost.localdomain ([113.29.230.82]) by smtp.gmail.com with ESMTPSA id a5sm29297285pfc.89.2016.08.26.07.32.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Aug 2016 07:32:59 -0700 (PDT) From: Jun Nie To: arnd@arndb.de, arm@kernel.org, linux-arm-kernel@lists.infradead.org, shawn.guo@linaro.org Subject: [PATCH v2 2/3] arm64: dts: Add ZTE ZX296718 SoC dts and Makefile Date: Fri, 26 Aug 2016 22:32:11 +0800 Message-Id: <1472221932-6730-3-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1472221932-6730-1-git-send-email-jun.nie@linaro.org> References: <1472221932-6730-1-git-send-email-jun.nie@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160826_073321_751607_CC68627B X-CRM114-Status: GOOD ( 15.33 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400e:c03:0:0:0:22d listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, jason.liu@linaro.org, Jun Nie MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Add device tree support for ZX296718 SoC and evaluation board based on it. Also document new values. Reviewed-by: Mark Rutland Signed-off-by: Jun Nie --- Documentation/devicetree/bindings/arm/zte.txt | 24 +++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/zte/Makefile | 5 + arch/arm64/boot/dts/zte/zx296718.dts | 21 +++ arch/arm64/boot/dts/zte/zx296718.dtsi | 253 ++++++++++++++++++++++++++ 5 files changed, 304 insertions(+) create mode 100644 arch/arm64/boot/dts/zte/Makefile create mode 100644 arch/arm64/boot/dts/zte/zx296718.dts create mode 100644 arch/arm64/boot/dts/zte/zx296718.dtsi -- 1.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/Documentation/devicetree/bindings/arm/zte.txt b/Documentation/devicetree/bindings/arm/zte.txt index 3ff5c9e..b80790a 100644 --- a/Documentation/devicetree/bindings/arm/zte.txt +++ b/Documentation/devicetree/bindings/arm/zte.txt @@ -13,3 +13,27 @@ Low power management required properties: Bus matrix required properties: - compatible = "zte,zx-bus-matrix" + + +--------------------------------------- +- ZX296718 SoC: + Required root node properties: + - compatible = "zte,zx296718" + +ZX296718 EVB board: + - "zte,zx296718-evb" + +System management required properties: + - compatible = "zte,zx296718-aon-sysctrl" + - compatible = "zte,zx296718-sysctrl" + +Example: +aon_sysctrl: aon-sysctrl@116000 { + compatible = "zte,zx296718-aon-sysctrl", "syscon"; + reg = <0x116000 0x1000>; +}; + +sysctrl: sysctrl@0x1463000 { + compatible = "zte,zx296718-sysctrl", "syscon"; + reg = <0x1463000 0x1000>; +}; diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 6e199c9..6684f97 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -19,6 +19,7 @@ dts-dirs += socionext dts-dirs += sprd dts-dirs += xilinx dts-dirs += lg +dts-dirs += zte subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/zte/Makefile b/arch/arm64/boot/dts/zte/Makefile new file mode 100644 index 0000000..a99640b --- /dev/null +++ b/arch/arm64/boot/dts/zte/Makefile @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_ZX) += zx296718.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb diff --git a/arch/arm64/boot/dts/zte/zx296718.dts b/arch/arm64/boot/dts/zte/zx296718.dts new file mode 100644 index 0000000..046cee3 --- /dev/null +++ b/arch/arm64/boot/dts/zte/zx296718.dts @@ -0,0 +1,21 @@ +/* + * ZTE Ltd. zx296718 Plaform + * + */ +/dts-v1/; +#include "zx296718.dtsi" + +/ { + model = "ZTE zx296718 evaluation board"; + compatible = "zte,zx296718-evb", "zte,zx296718"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + +}; diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi new file mode 100644 index 0000000..aba4a7d --- /dev/null +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi @@ -0,0 +1,253 @@ +/* + * DTS File for ZTE ZX296718 Plaform + * + * Copyright (c) 2016 ZTE Semiconductor Co., Ltd. + */ +#include +#include +#include + +/ { + compatible = "zte,zx296718"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + osc12m: osc12m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + clock-output-names = "osc12m"; + }; + + osc24m: osc24m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc24m"; + }; + + osc25m: osc25m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "osc25m"; + }; + + clk24k: clk-24k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000>; + clock-output-names = "zte:rtcclk"; + }; + + osc32k: osc32k_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "osc32k"; + }; + + osc60m: osc60m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + clock-output-names = "osc60m"; + }; + + osc99m: osc99m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <99000000>; + clock-output-names = "osc99m"; + }; + + osc125m: osc125m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "osc125m"; + }; + + osc198m: osc198m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <198000000>; + clock-output-names = "osc198m"; + }; + + pll_vga: pll_1073m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1073000000>; + clock-output-names = "pll_vga"; + }; + + pll_ddr: pll_932m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <932000000>; + clock-output-names = "pll_ddr"; + }; + + pll_mac: pll_1000m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + clock-output-names = "pll_mac"; + }; + + pll_mm0: pll_1188m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1188000000>; + clock-output-names = "pll_mm0"; + }; + + pll_mm1: pll_1296m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1296000000>; + clock-output-names = "pll_mm1"; + }; + + pll_audio: pll_884m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <884000000>; + clock-output-names = "pll_audio"; + }; + + pll_hsic: pll_960m_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <960000000>; + clock-output-names = "pll_hsic"; + }; + + gic: interrupt-controller@2a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + #redistributor-regions = <6>; + redistributor-stride = <0x0 0x40000>; + interrupt-controller; + reg = <0x02a00000 0x10000>, + <0x02b00000 0x20000>, + <0x02b20000 0x20000>, + <0x02b40000 0x20000>, + <0x02b60000 0x20000>, + <0x02b80000 0x20000>, + <0x02ba0000 0x20000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + aon_sysctrl: aon-sysctrl@116000 { + compatible = "zte,zx296718-aon-sysctrl", "syscon"; + reg = <0x116000 0x1000>; + }; + + sysctrl: sysctrl@0x1463000 { + compatible = "zte,zx296718-sysctrl", "syscon"; + reg = <0x1463000 0x1000>; + }; + + uart0: uart@11f000 { + compatible = "arm,pl011", "arm,primecell"; + arm,primecell-periphid = <0x001feffe>; + reg = <0x11f000 0x1000>; + interrupts = ; + clocks = <&osc24m>; + clock-names = "apb_pclk"; + }; + + dma: dma-controller@01460000 { + compatible = "zte,zx296702-dma"; + reg = <0x01460000 0x1000>; + interrupts = ; + clocks = <&osc24m>; + clock-names = "dmaclk"; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <32>; + }; + }; +};