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[2001:1868:205::9]) by mx.google.com with ESMTPS id xe10si9940986pab.50.2016.08.24.07.40.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Aug 2016 07:40:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bcZL6-0007IT-Qw; Wed, 24 Aug 2016 14:39:36 +0000 Received: from mail-wm0-x22e.google.com ([2a00:1450:400c:c09::22e]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bcZIN-0005Kd-46 for linux-arm-kernel@lists.infradead.org; Wed, 24 Aug 2016 14:36:52 +0000 Received: by mail-wm0-x22e.google.com with SMTP id o80so31369438wme.1 for ; Wed, 24 Aug 2016 07:36:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1HSIwV/2oGJNcaFoGu0z7pzySqOWH2J/szMR6XwPb34=; b=Rf0bw9etkFNnLtbTzGWvnbu/6wmb8ACae7FHkJOkrHhgs94kCmCcT0+WOYQNwSUJHv o4f+Uino4DLsAVvvHeu1wYu9Dbd5Lk7007TnAxwf6ZKRNYnIUvcxentj3Vp9rFCM2/t2 p8tj/Fzgmf1zu96avnX8f9IZNm7YRiHJmjGm0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1HSIwV/2oGJNcaFoGu0z7pzySqOWH2J/szMR6XwPb34=; b=eBSZRBCDIb1BHW2sAs+NmHlvOmQPExBtYkvh5UzSulQVPWBE0ztpyeg7qRs0/52FNY YA09FC3CdWStV1UVnSkvCH9wCDeZL3mDGjF/JvQFUNasYQ5Eo1SN/e3nb8Fj1jGh5BoX GDCFcH4G2NzO4D8jE6zIKkw5wcwNm6YYIhWwAT0Kwk31wZ7tJM0r4SZtgBAMyaacV+rs 5SDWKEZSXSjIxl/gf9+svSFNxUlFWmB8frcO848h98F1Mh+DFw0vV4EXg9w4YDiA+l4R a+KTtwEscpQDufmk+JZuj3Rt931t0sLG+AGcRyxrJL/IRj5dlDA2sAs6Ol/iMgV+s2+d ML2Q== X-Gm-Message-State: AE9vXwOcvOe7sA+4rbhIB+2IMaATgKRsklZiL2vS1JIrLsaoyU53jinDf9qAvlnSLuGr4p/c X-Received: by 10.28.22.6 with SMTP id 6mr3515140wmw.55.1472049385347; Wed, 24 Aug 2016 07:36:25 -0700 (PDT) Received: from localhost.localdomain ([213.143.60.123]) by smtp.gmail.com with ESMTPSA id n2sm10365569wjd.1.2016.08.24.07.36.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Aug 2016 07:36:24 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will.deacon@arm.com, mark.rutland@arm.com, james.morse@arm.com Subject: [PATCH v2 6/9] arm64: call __enable_mmu as an ordinary function for secondary/resume Date: Wed, 24 Aug 2016 16:36:03 +0200 Message-Id: <1472049366-10922-7-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472049366-10922-1-git-send-email-ard.biesheuvel@linaro.org> References: <1472049366-10922-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160824_073647_607468_B62BB5CF X-CRM114-Status: GOOD ( 11.68 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:400c:c09:0:0:0:22e listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org This updates the secondary and cpu_resume call sites to simply call __enable_mmu as an ordinary function, with a bl instruction. This requires the callers to be covered by .idmap.text. Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 14 ++++++-------- arch/arm64/kernel/sleep.S | 10 +++------- 2 files changed, 9 insertions(+), 15 deletions(-) -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel Reviewed-by: Mark Rutland diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 3e08e51578d5..c112c153821e 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -634,6 +634,7 @@ ENTRY(__boot_cpu_mode) * This provides a "holding pen" for platforms to hold all secondary * cores are held until we're ready for them to initialise. */ + .pushsection ".idmap.text", "ax" ENTRY(secondary_holding_pen) bl el2_setup // Drop to EL1, w0=cpu_boot_mode bl set_cpu_boot_mode_flag @@ -663,10 +664,12 @@ secondary_startup: * Common entry point for secondary CPUs. */ bl __cpu_setup // initialise processor - - adr_l lr, __secondary_switch // address to jump to after enabling the MMU - b __enable_mmu + bl __enable_mmu + ldr x8, =__secondary_switched + br x8 ENDPROC(secondary_startup) + .ltorg + .popsection __secondary_switched: adr_l x5, vectors @@ -812,8 +815,3 @@ __primary_switch: ldr x8, =__primary_switched br x8 ENDPROC(__primary_switch) - -__secondary_switch: - ldr x8, =__secondary_switched - br x8 -ENDPROC(__secondary_switch) diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S index 4bce95cd656a..1d4aba6fcc7a 100644 --- a/arch/arm64/kernel/sleep.S +++ b/arch/arm64/kernel/sleep.S @@ -95,19 +95,15 @@ ENTRY(__cpu_suspend_enter) ret ENDPROC(__cpu_suspend_enter) + .pushsection ".idmap.text", "ax" ENTRY(cpu_resume) bl el2_setup // if in EL2 drop to EL1 cleanly bl __cpu_setup /* enable the MMU early - so we can access sleep_save_stash by va */ - adr_l lr, _resume_switched /* __enable_mmu will branch here */ - b __enable_mmu -ENDPROC(cpu_resume) - - .pushsection ".idmap.text", "ax" -_resume_switched: + bl __enable_mmu ldr x8, =_cpu_resume br x8 -ENDPROC(_resume_switched) +ENDPROC(cpu_resume) .ltorg .popsection