From patchwork Fri Aug 12 15:27:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 73849 Delivered-To: patch@linaro.org Received: by 10.140.29.52 with SMTP id a49csp230185qga; Fri, 12 Aug 2016 08:29:30 -0700 (PDT) X-Received: by 10.98.77.70 with SMTP id a67mr27999450pfb.151.1471015770080; Fri, 12 Aug 2016 08:29:30 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id e22si9431174pfd.76.2016.08.12.08.29.29 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Aug 2016 08:29:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bYENj-0001p2-5H; Fri, 12 Aug 2016 15:28:23 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bYENd-0001in-NP for linux-arm-kernel@lists.infradead.org; Fri, 12 Aug 2016 15:28:18 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1B5A0431; Fri, 12 Aug 2016 08:29:27 -0700 (PDT) Received: from e104818-lin.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 764173F213; Fri, 12 Aug 2016 08:27:56 -0700 (PDT) From: Catalin Marinas To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/7] arm64: Factor out TTBR0_EL1 setting into a specific asm macro Date: Fri, 12 Aug 2016 16:27:41 +0100 Message-Id: <1471015666-23125-3-git-send-email-catalin.marinas@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1471015666-23125-1-git-send-email-catalin.marinas@arm.com> References: <1471015666-23125-1-git-send-email-catalin.marinas@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160812_082817_836389_6993A5AA X-CRM114-Status: UNSURE ( 7.85 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -8.3 (--------) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-8.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -1.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Morse , Will Deacon , Kees Cook , kernel-hardening@lists.openwall.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org This patch takes the TTBR0_EL1 setting code out of cpu_do_switch_mm into a dedicated cpu_set_ttbr0 macro which will be reused in a subsequent patch. Cc: Will Deacon Cc: James Morse Cc: Kees Cook Signed-off-by: Catalin Marinas --- arch/arm64/include/asm/assembler.h | 25 +++++++++++++++++++++++++ arch/arm64/mm/proc.S | 16 +--------------- 2 files changed, 26 insertions(+), 15 deletions(-) _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index bbed373f4ab7..039db634a693 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -352,6 +352,31 @@ alternative_endif .endm /* + * TTBR0_EL1 update macro. + */ + .macro cpu_set_ttbr0, ttbr0, errata = 0, ret = 0 + msr ttbr0_el1, \ttbr0 + isb + .if \errata +alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 + .if \ret + ret + .endif + nop + nop + nop +alternative_else + ic iallu + dsb nsh + isb + .if \ret + ret + .endif +alternative_endif + .endif + .endm + +/* * User access enabling/disabling macros. */ .macro uaccess_disable, tmp1 diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 5bb61de23201..442ade0f44eb 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -25,8 +25,6 @@ #include #include #include -#include -#include #ifdef CONFIG_ARM64_64K_PAGES #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K @@ -123,19 +121,7 @@ ENDPROC(cpu_do_resume) ENTRY(cpu_do_switch_mm) mmid x1, x1 // get mm->context.id bfi x0, x1, #48, #16 // set the ASID - msr ttbr0_el1, x0 // set TTBR0 - isb -alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 - ret - nop - nop - nop -alternative_else - ic iallu - dsb nsh - isb - ret -alternative_endif + cpu_set_ttbr0 x0, errata = 1, ret = 1 ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "ax"