From patchwork Thu Apr 21 08:18:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Murzin X-Patchwork-Id: 66335 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2937qge; Thu, 21 Apr 2016 01:21:50 -0700 (PDT) X-Received: by 10.98.36.26 with SMTP id r26mr18518855pfj.99.1461226910759; Thu, 21 Apr 2016 01:21:50 -0700 (PDT) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [198.137.202.9]) by mx.google.com with ESMTPS id rw1si2358185pab.58.2016.04.21.01.21.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Apr 2016 01:21:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 198.137.202.9 as permitted sender) client-ip=198.137.202.9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 198.137.202.9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9qy-0001aw-Gr; Thu, 21 Apr 2016 08:20:48 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1at9pi-0007Jx-JB for linux-arm-kernel@lists.infradead.org; Thu, 21 Apr 2016 08:19:34 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DE37B524; Thu, 21 Apr 2016 01:17:35 -0700 (PDT) Received: from login1.euhpc.arm.com (login1.euhpc.arm.com [10.6.26.143]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B88E33F218; Thu, 21 Apr 2016 01:18:51 -0700 (PDT) From: Vladimir Murzin To: linux@arm.linux.org.uk Subject: [PATCH RFC 05/10] ARM: Extract cp15 operations from cache flush code Date: Thu, 21 Apr 2016 09:18:17 +0100 Message-Id: <1461226702-27160-6-git-send-email-vladimir.murzin@arm.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1461226702-27160-1-git-send-email-vladimir.murzin@arm.com> References: <1461226702-27160-1-git-send-email-vladimir.murzin@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160421_011930_860256_C11E4B82 X-CRM114-Status: GOOD ( 18.16 ) X-Spam-Score: -7.9 (-------) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-7.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -1.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mcoquelin.stm32@gmail.com, manabian@gmail.com, stefan@agner.ch, kbuild-all@01.org, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Jonathan Austin Caches have been added to the V7M architecture. Instead of CP15 operations, the cache maintenance is done with memory-mapped registers. Other properties of the cache architecture are the same as V7A/R. In order to make it possible to use the same cacheflush code on V7A/R and V7M, this commit separates out the cp15 cache maintenance operations into a separate, V7A/R specific v7 cache macros file. This is done by introducing cache macros. This commit does not introduce any V7M-related code to simplify the process of verifying that the result of compiling cache-v7.S is identical before and after this commit. Signed-off-by: Jonathan Austin Signed-off-by: Vladimir Murzin --- arch/arm/mm/cache-v7.S | 51 ++++++++--------- arch/arm/mm/proc-macros.S | 23 -------- arch/arm/mm/proc-v7.S | 1 + arch/arm/mm/v7-cache-macros.S | 124 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 147 insertions(+), 52 deletions(-) create mode 100644 arch/arm/mm/v7-cache-macros.S -- 1.7.9.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index a134d8a..53a802e 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -17,6 +17,7 @@ #include #include "proc-macros.S" +#include "v7-cache-macros.S" /* * The secondary kernel init calls v7_flush_dcache_all before it enables @@ -33,9 +34,9 @@ */ ENTRY(v7_invalidate_l1) mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 + write_csselr r0 + read_ccsidr r0 movw r1, #0x7fff and r2, r1, r0, lsr #13 @@ -55,7 +56,7 @@ ENTRY(v7_invalidate_l1) mov r5, r3, lsl r1 mov r6, r2, lsl r0 orr r5, r5, r6 @ Reg = (Temp< #include "proc-macros.S" +#include "v7-cache-macros.S" #ifdef CONFIG_ARM_LPAE #include "proc-v7-3level.S" diff --git a/arch/arm/mm/v7-cache-macros.S b/arch/arm/mm/v7-cache-macros.S new file mode 100644 index 0000000..5212383 --- /dev/null +++ b/arch/arm/mm/v7-cache-macros.S @@ -0,0 +1,124 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2012 ARM Limited + * + * Author: Jonathan Austin + */ + +.macro read_ctr, rt + mrc p15, 0, \rt, c0, c0, 1 +.endm + +.macro read_ccsidr, rt + mrc p15, 1, \rt, c0, c0, 0 +.endm + +.macro read_clidr, rt + mrc p15, 1, \rt, c0, c0, 1 +.endm + +.macro write_csselr, rt + mcr p15, 2, \rt, c0, c0, 0 +.endm + +/* + * dcisw: invalidate data cache by set/way + */ +.macro dcisw, rt + mcr p15, 0, \rt, c7, c6, 2 +.endm + +/* + * dccisw: clean and invalidate data cache by set/way + */ +.macro dccisw, rt + mcr p15, 0, \rt, c7, c14, 2 +.endm + +/* + * dccimvac: Clean and invalidate data cache line by MVA to PoC. + */ +.macro dccimvac, rt, cond = al + mcr\cond p15, 0, \rt, c7, c14, 1 +.endm + +/* + * dcimvac: Invalidate data cache line by MVA to PoC + */ +.macro dcimvac, rt + mcr p15, 0, r0, c7, c6, 1 +.endm + +/* + * dccmvau: Clean data cache line by MVA to PoU + */ +.macro dccmvau, rt + mcr p15, 0, \rt, c7, c11, 1 +.endm + +/* + * dccmvac: Clean data cache line by MVA to PoC + */ +.macro dccmvac, rt + mcr p15, 0, \rt, c7, c10, 1 +.endm + +/* + * icimvau: Invalidate instruction caches by MVA to PoU + */ +.macro icimvau, rt + mcr p15, 0, \rt, c7, c5, 1 +.endm + +/* + * Invalidate the icache, inner shareable if SMP, invalidate BTB for UP. + */ +.macro invalidate_icache, rt + mov \rt, #0 + ALT_SMP(mcr p15, 0, \rt, c7, c1, 0) @ icialluis: I-cache invalidate inner shareable + ALT_UP(mcr p15, 0, \rt, c7, c5, 0) @ iciallu: I+BTB cache invalidate +.endm + +/* + * Invalidate the BTB, inner shareable if SMP. + */ +.macro invalidate_bp, rt + mov \rt, #0 + ALT_SMP(mcr p15, 0, \rt, c7, c1, 6) @ bpiallis: invalidate BTB inner shareable + ALT_UP(mcr p15, 0, \rt, c7, c5, 6) @ bpiall: invalidate BTB +.endm + +/* + * dcache_line_size - get the minimum D-cache line size from the CTR register + * on ARMv7. + */ + .macro dcache_line_size, reg, tmp + read_ctr \tmp + lsr \tmp, \tmp, #16 + and \tmp, \tmp, #0xf @ cache line size encoding + mov \reg, #4 @ bytes per word + mov \reg, \reg, lsl \tmp @ actual cache line size + .endm + +/* + * icache_line_size - get the minimum I-cache line size from the CTR register + * on ARMv7. + */ + .macro icache_line_size, reg, tmp + read_ctr \tmp + and \tmp, \tmp, #0xf @ cache line size encoding + mov \reg, #4 @ bytes per word + mov \reg, \reg, lsl \tmp @ actual cache line size + .endm