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[2001:1868:205::9]) by mx.google.com with ESMTPS id w9si2163650pfi.224.2016.04.04.07.54.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Apr 2016 07:54:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1an5se-0005Jx-AV; Mon, 04 Apr 2016 14:53:28 +0000 Received: from mail-lb0-x22f.google.com ([2a00:1450:4010:c04::22f]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1an5sC-00056s-Fj for linux-arm-kernel@lists.infradead.org; Mon, 04 Apr 2016 14:53:01 +0000 Received: by mail-lb0-x22f.google.com with SMTP id u8so164705366lbk.0 for ; Mon, 04 Apr 2016 07:52:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tJPz5HgeP+4ZyIWMAvefC3wBdIokqmO3miQ0QAUQf+4=; b=OpvR++x1BUL1Li2gTvOlTXPQ/jL8Mm59NxmAlt6hBH0FF8BAhbRWdKmCCZ1fefPzJj ZAH113bbyJ8WJuR2uFMwJykhJG9rOkeEtNulV1YPrPdJ63hz6E2cgxgbMVZ6Idqu5rmy mt6Rrdbb0Fo4K9b8CiX2LO8Wsp787TpVqzA74= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tJPz5HgeP+4ZyIWMAvefC3wBdIokqmO3miQ0QAUQf+4=; b=D73AOOMh2TuXZn+XWYFN8iNJPs+zwL1JL4uSzBIGsgtcFwNDnZXConzNv54agLZ5RD SAAp08kg0uqB8jFgB35WYd7Gnt41N3niPinqoJs8TuQTSNcx9Qh7h2lhdNjkxNWH5dfW WdZ3nGNpCPyFzImsOPt6DApIm/AngTx+gT4wxY0JOuEv2IxA3hz0DlJIri9o68cvELzf KPdmxfPeDw/Z5gKA3JJgafl7UL1MBJ4QYZ2mjBSC8SJr5+948vXyMcuXA0rE7+XFrJJQ b3UdsgL67j2zxN5uh+bNmfIC9PbXH1jROVEACJcT1jgINEvpD4ZKif8/BwSPl6BmuDcX B8rg== X-Gm-Message-State: AD7BkJLZIgEAmZsCtw6qVX1NQTeFyMPrHBEJVzvjbQbvglclVckPBO0/L039ut4jbzJkW92j X-Received: by 10.28.127.80 with SMTP id a77mr12482260wmd.84.1459781557542; Mon, 04 Apr 2016 07:52:37 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id cf6sm7922528wjc.12.2016.04.04.07.52.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 04 Apr 2016 07:52:36 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, will.deacon@arm.com, catalin.marinas@arm.com, mark.rutland@arm.com Subject: [PATCH 4/8] arm64/kernel: use ordinary calling convention for EL2 setup Date: Mon, 4 Apr 2016 16:52:20 +0200 Message-Id: <1459781544-14310-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1459781544-14310-1-git-send-email-ard.biesheuvel@linaro.org> References: <1459781544-14310-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160404_075300_846992_E18A8F59 X-CRM114-Status: GOOD ( 11.81 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:4010:c04:0:0:0:22f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Since the return value of el2_setup() is almost immediately passed to set_cpu_boot_mode_flag() in all cases, there is no need to use a callee saved register w20, but we can use simply use w0 instead. Signed-off-by: Ard Biesheuvel --- arch/arm64/kernel/head.S | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) -- 2.5.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index f441fc73a7a2..2a1b3ba1d81c 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -211,7 +211,7 @@ section_table: ENTRY(stext) bl preserve_boot_args - bl el2_setup // Drop to EL1, w20=cpu_boot_mode + bl el2_setup // Drop to EL1, w0=cpu_boot_mode mov x23, xzr // KASLR offset, defaults to 0 adrp x24, __PHYS_OFFSET bl set_cpu_boot_mode_flag @@ -530,7 +530,7 @@ CPU_LE( bic x0, x0, #(1 << 25) ) // Clear the EE bit for EL2 CPU_BE( orr x0, x0, #(3 << 24) ) // Set the EE and E0E bits for EL1 CPU_LE( bic x0, x0, #(3 << 24) ) // Clear the EE and E0E bits for EL1 msr sctlr_el1, x0 - mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 + mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 isb ret @@ -616,7 +616,7 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems cbz x2, install_el2_stub - mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 + mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 isb ret @@ -631,20 +631,20 @@ install_el2_stub: PSR_MODE_EL1h) msr spsr_el2, x0 msr elr_el2, lr - mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 + mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 eret ENDPROC(el2_setup) /* * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed - * in x20. See arch/arm64/include/asm/virt.h for more info. + * in x0. See arch/arm64/include/asm/virt.h for more info. */ ENTRY(set_cpu_boot_mode_flag) adr_l x1, __boot_cpu_mode - cmp w20, #BOOT_CPU_MODE_EL2 + cmp w0, #BOOT_CPU_MODE_EL2 b.ne 1f add x1, x1, #4 -1: str w20, [x1] // This CPU has booted in EL1 +1: str w0, [x1] // This CPU has booted in EL1 dmb sy dc ivac, x1 // Invalidate potentially stale cache line ret @@ -669,7 +669,7 @@ ENTRY(__boot_cpu_mode) * cores are held until we're ready for them to initialise. */ ENTRY(secondary_holding_pen) - bl el2_setup // Drop to EL1, w20=cpu_boot_mode + bl el2_setup // Drop to EL1, w0=cpu_boot_mode bl set_cpu_boot_mode_flag mrs x0, mpidr_el1 ldr x1, =MPIDR_HWID_BITMASK