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[2001:1868:205::9]) by mx.google.com with ESMTPS id z25si6211428pfa.170.2016.03.30.05.27.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Mar 2016 05:27:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1alFD0-0006cZ-Dv; Wed, 30 Mar 2016 12:26:50 +0000 Received: from mail-wm0-x236.google.com ([2a00:1450:400c:c09::236]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1alFCZ-0006QC-Iz for linux-arm-kernel@lists.infradead.org; Wed, 30 Mar 2016 12:26:26 +0000 Received: by mail-wm0-x236.google.com with SMTP id p65so180740354wmp.1 for ; Wed, 30 Mar 2016 05:26:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WQIUwvpRLijTzLuiTAEUebOywtH57ESKQqs4Q/HMTzI=; b=gcfknJe4mGVoiaQole36ESZCUDE4EFg05Tg29lBGPyn6QEw57x+YD9xmRxah81zIgX b/uBxEkDpViAk0z20QorNSfqChmzw3rQJ4aTlc4LrzUNgxJ6/9qKm3Al5OAyu9e5XYod SuMwLHAzopEHWOd6646AVdIukqz9dkYtk4gTc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WQIUwvpRLijTzLuiTAEUebOywtH57ESKQqs4Q/HMTzI=; b=mI5MoEfl0UArzzhJkMBKJIPUSWb3/e+0tmLgROFgMAmlM1OAIGpWR23tzw93J6phk+ dxv6ZPQqMZ3Ls+SfQFUhrDctWQMWTQoAn+GTpBily4JEeszxJny7pKehqvmbKdPN49Cg pONH8w4OQpG2lU3YCoZx7eGxf610UX7ruFbiF6yQ2ddrwxJyy/4DVAc3AOj0t/cHo8zN 3Alfa9RMIfKLI5sSN1cymonITql7+wJLqAkFzKBf6LIbFibIsQL9DtTjRKXCC+q00FFB JtCr5SpvvEK83y9/YzxojnyVoNhq0sDrQqwaajBEv5zFpeq9C+Nll/A6kjdNd5UB+Z9E 5fKA== X-Gm-Message-State: AD7BkJIiQ1v7uT6QVL8/IwX8KyQrbIv3Hgr0iX7iRTfNZ7gs0cjRV/i/npJwYoRWykPYQfaP X-Received: by 10.28.176.133 with SMTP id z127mr23999426wme.66.1459340762124; Wed, 30 Mar 2016 05:26:02 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id u14sm19502511wmu.8.2016.03.30.05.25.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Mar 2016 05:26:01 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com Subject: [PATCH v2 2/3] arm64: choose memstart_addr based on minimum sparsemem section alignment Date: Wed, 30 Mar 2016 14:25:47 +0200 Message-Id: <1459340748-14975-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1459340748-14975-1-git-send-email-ard.biesheuvel@linaro.org> References: <1459340748-14975-1-git-send-email-ard.biesheuvel@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160330_052623_985912_7E921F99 X-CRM114-Status: GOOD ( 10.55 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:400c:c09:0:0:0:236 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, will.deacon@arm.com, Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org This redefines ARM64_MEMSTART_ALIGN in terms of the minimal alignment required by sparsemem vmemmap. This comes down to using 1 GB for all translation granules if CONFIG_SPARSEMEM_VMEMMAP is enabled. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/kernel-pgtable.h | 21 +++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) -- 2.5.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h index 5c6375d8528b..7e51d1b57c0c 100644 --- a/arch/arm64/include/asm/kernel-pgtable.h +++ b/arch/arm64/include/asm/kernel-pgtable.h @@ -19,6 +19,7 @@ #ifndef __ASM_KERNEL_PGTABLE_H #define __ASM_KERNEL_PGTABLE_H +#include /* * The linear mapping and the start of memory are both 2M aligned (per @@ -86,10 +87,24 @@ * (64k granule), or a multiple that can be mapped using contiguous bits * in the page tables: 32 * PMD_SIZE (16k granule) */ -#ifdef CONFIG_ARM64_64K_PAGES -#define ARM64_MEMSTART_ALIGN SZ_512M +#if defined(CONFIG_ARM64_4K_PAGES) +#define ARM64_MEMSTART_SHIFT PUD_SHIFT +#elif defined(CONFIG_ARM64_16K_PAGES) +#define ARM64_MEMSTART_SHIFT (PMD_SHIFT + 5) #else -#define ARM64_MEMSTART_ALIGN SZ_1G +#define ARM64_MEMSTART_SHIFT PMD_SHIFT +#endif + +/* + * sparsemem vmemmap imposes an additional requirement on the alignment of + * memstart_addr, due to the fact that the base of the vmemmap region + * has a direct correspondence, and needs to appear sufficiently aligned + * in the virtual address space. + */ +#if defined(CONFIG_SPARSEMEM_VMEMMAP) && ARM64_MEMSTART_SHIFT < SECTION_SIZE_BITS +#define ARM64_MEMSTART_ALIGN (1UL << SECTION_SIZE_BITS) +#else +#define ARM64_MEMSTART_ALIGN (1UL << ARM64_MEMSTART_SHIFT) #endif #endif /* __ASM_KERNEL_PGTABLE_H */