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[2001:1868:205::9]) by mx.google.com with ESMTPS id v67si2024252pfa.181.2016.03.25.02.38.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Mar 2016 02:38:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ajOBe-0005ue-WA; Fri, 25 Mar 2016 09:37:47 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ajOAy-0005dY-J2 for linux-arm-kernel@lists.infradead.org; Fri, 25 Mar 2016 09:37:07 +0000 Received: from 172.24.1.60 (EHLO szxeml430-hub.china.huawei.com) ([172.24.1.60]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DHP56273; Fri, 25 Mar 2016 17:36:01 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml430-hub.china.huawei.com (10.82.67.185) with Microsoft SMTP Server id 14.3.235.1; Fri, 25 Mar 2016 17:35:47 +0800 From: Kefeng Wang To: Catalin Marinas , "Suzuki K . Poulose" Subject: [RFC PATCH 3/3] arm64: Expose cpu vender id and model name through cpuinfo Date: Fri, 25 Mar 2016 17:30:09 +0800 Message-ID: <1458898209-7486-4-git-send-email-wangkefeng.wang@huawei.com> X-Mailer: git-send-email 2.6.0.GIT In-Reply-To: <1458898209-7486-1-git-send-email-wangkefeng.wang@huawei.com> References: <1458898209-7486-1-git-send-email-wangkefeng.wang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.56F50681.00EF, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d0a2dccb8839924e31162a1b76b2fb41 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160325_023705_372067_CB5E1686 X-CRM114-Status: GOOD ( 11.75 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , wangkefeng.wang@huawei.com, Will Deacon , linux-arm-kernel@lists.infradead.org, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org It is helpful to show the name of chip vendor and CPU model to customers in cpuinfo, identify them by using CPU implementer and CPU part is not intuitive(compared with x86). We are complained for this several times, so expose them. Signed-off-by: Kefeng Wang --- arch/arm64/include/asm/cpu.h | 2 ++ arch/arm64/kernel/cpuinfo.c | 62 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) -- 1.7.12.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 13a6103..b8c3d79 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -25,6 +25,8 @@ */ struct cpuinfo_arm64 { struct cpu cpu; + char vendor[16]; + char model_name[16]; u32 reg_ctr; u32 reg_cntfrq; u32 reg_dczid; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 488d49a..da5f7df 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -100,6 +101,62 @@ static const char *const compat_hwcap2_str[] = { }; #endif /* CONFIG_COMPAT */ +static void cpuinfo_get_vendor_model(struct cpuinfo_arm64 *info) +{ + char *vendor = info->vendor; + char *name = info->model_name; + u32 midr = info->reg_midr; + u32 impl = MIDR_IMPLEMENTOR(midr); + u32 part = MIDR_PARTNUM(midr); + + switch (impl) { + case ARM_CPU_IMP_ARM: + strcpy(vendor, "ARM"); + switch (part) { + case ARM_CPU_PART_AEM_V8: + strcpy(name, "AEM-V8"); + break; + case ARM_CPU_PART_FOUNDATION: + strcpy(name, "Foundation"); + break; + case ARM_CPU_PART_CORTEX_A53: + strcpy(name, "Cortex-A53"); + break; + case ARM_CPU_PART_CORTEX_A57: + strcpy(name, "Cortex-A57"); + break; + }; + break; + case ARM_CPU_IMP_APM: + strcpy(vendor, "APM"); + switch (part) { + case APM_CPU_PART_POTENZA: + strcpy(name, "Potenza"); + break; + }; + break; + case ARM_CPU_IMP_CAVIUM: + strcpy(vendor, "CAVIUM"); + switch (part) { + case CAVIUM_CPU_PART_THUNDERX: + strcpy(name, "Thunderx"); + break; + }; + break; + case ARM_CPU_IMP_BRCM: + strcpy(vendor, "BROADCOM"); + switch (part) { + case BRCM_CPU_PART_VULCAN: + strcpy(name, "Vulcan"); + break; + }; + break; + default: + strcpy(vendor, "Unknown"); + strcpy(name, "Unknown"); + } +} + static int c_show(struct seq_file *m, void *v) { int i, j; @@ -116,6 +173,9 @@ static int c_show(struct seq_file *m, void *v) * "processor". Give glibc what it expects. */ seq_printf(m, "processor\t: %d\n", i); + seq_printf(m, "vendor_id\t: %s\n", cpuinfo->vendor); + seq_printf(m, "model name\t: %s rev %d (%s)\n", cpuinfo->model_name, + MIDR_REVISION(midr), ELF_PLATFORM); seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", loops_per_jiffy / (500000UL/HZ), @@ -238,6 +298,8 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_mvfr1 = read_cpuid(MVFR1_EL1); info->reg_mvfr2 = read_cpuid(MVFR2_EL1); + cpuinfo_get_vendor_model(info); + cpuinfo_detect_icache_policy(info); check_local_cpu_errata();