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[2001:1868:205::9]) by mx.google.com with ESMTPS id f63si3529287pfj.137.2016.02.24.00.50.40 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Feb 2016 00:50:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aYV89-0002R2-LZ; Wed, 24 Feb 2016 08:49:09 +0000 Received: from mail-lb0-x236.google.com ([2a00:1450:4010:c04::236]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aYV84-0002O9-Dn for linux-arm-kernel@lists.infradead.org; Wed, 24 Feb 2016 08:49:06 +0000 Received: by mail-lb0-x236.google.com with SMTP id x4so6371235lbm.0 for ; Wed, 24 Feb 2016 00:48:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=y6TmAAzuXdt5/CPDZhfI3DY23CN1BunVjZ9Ppo9mzbg=; b=eo0qwkhGj+V2ScbGhxZOVN3HYI4yF4ihefoYWOi9bf+xcMI8FCYe34vl5c8T9VpY9q X+QbK2tjjOShQYxmtiZOsz55l+/yS+6G0Ta01gBuR1lZMmGOcPufo0dk2kvZpJAGjPtu bZLNKnlNQF+TmV887HNRl/iw5JIXup5Fk6CvY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=y6TmAAzuXdt5/CPDZhfI3DY23CN1BunVjZ9Ppo9mzbg=; b=LQS6kyBl5yShKaHM/4ayROr5KsDSKkDh5rcWqtdmCkdjJ2tCHzNBURru2kiuaOymVc M22B+czxOiPZLETQ7xvXzr6YjPtnM1cxg3/NnT+ntAlxiHiKYImHmbSbUtnjpePV2DqK Bgkeqy+XrdFfQwNLZMJ2I+TAOz/tEy8mdu8AIuSaqmTjQ1h7o9ni4lfNnPFKqzcT84Aq 0HcMT6UaQR84Hri2icD/JcTMYwf+iwaOBvHbI6fycDh8GAAV19kLmbvyZ/ig2758fr4s QPwdllSKO3OesaSG8JqP5VXb6vtOWr7fRwA5DIkFErbwsylRfL2DXj7lwN4ZIUPNKSq6 grGg== X-Gm-Message-State: AG10YOS/6UHBufclWg2DTfbdkBnikgTlqFK+9w4HuCvqRbMqY0Dp/8bpOUjbjTWXmxssNSYy X-Received: by 10.112.168.5 with SMTP id zs5mr14803762lbb.56.1456303720488; Wed, 24 Feb 2016 00:48:40 -0800 (PST) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id q10sm241079lfq.8.2016.02.24.00.48.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Feb 2016 00:48:39 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Peter Maydell Subject: [PATCH] ARM: realview: DT support for the PBA8 Date: Wed, 24 Feb 2016 09:48:34 +0100 Message-Id: <1456303714-31039-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160224_004905_013645_2C059914 X-CRM114-Status: GOOD ( 18.84 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:4010:c04:0:0:0:236 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Russell King , Pawel Moll , Marc Zyngier , Linus Walleij , Will Deacon MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org This adds a devicetree for the ARM RealView PBA8 platform, also known as HBI-0178, "RealView(R) Platform Baseboard for Cortex(TM)-A8". Tested in QEMU with -M realview-pb-a8 and works like a charm, however with these annoying boot messages: of_amba_device_create(): amba_device_add() failed (-19) for /soc/sysctl@10001000 of_amba_device_create(): amba_device_add() failed (-19) for /soc/ssp@1000d000 of_amba_device_create(): amba_device_add() failed (-19) for /soc/timer@10018000 of_amba_device_create(): amba_device_add() failed (-19) for /soc/timer@10019000 of_amba_device_create(): amba_device_add() failed (-19) for /soc/sysctl@1001a000 I think this is because these PrimeCells do not exist in the QEMU machine model but would work fine on the real hardware. QEMU still works, because the SP810 clocks will anyway probe, as they are not amba_devices but use the special CLK_OF_DECLARE() probing macro. Cc: Arnd Bergmann Cc: Pawel Moll Cc: Peter Maydell Cc: Marc Zyngier Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/arm-realview-pba8.dts | 620 ++++++++++++++++++++++++++++++++ 2 files changed, 622 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/arm-realview-pba8.dts -- 2.4.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 39deb1741465..bf01d0641531 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -537,7 +537,8 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-eb.dtb \ arm-realview-eb-11mp.dtb \ arm-realview-eb-11mp-revb.dtb \ - arm-realview-eb-a9mp.dtb + arm-realview-eb-a9mp.dtb \ + arm-realview-pba8.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3036-evb.dtb \ rk3036-kylin.dtb \ diff --git a/arch/arm/boot/dts/arm-realview-pba8.dts b/arch/arm/boot/dts/arm-realview-pba8.dts new file mode 100644 index 000000000000..722b29308720 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-pba8.dts @@ -0,0 +1,620 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include +#include +#include "skeleton.dtsi" + +/ { + model = "ARM RealView PB-A8"; + compatible = "arm,realview-pba8"; + arm,hbi = <0x178>; + + chosen { }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c; + }; + + memory { + /* 128 MiB memory @ 0x0 */ + reg = <0x00000000 0x08000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0>; + }; + }; + + pmu: pmu@0 { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + /* The voltage to the MMC card is hardwired at 3.3V */ + vmmc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + veth: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "veth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + refclk32khz: refclk32khz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + mclk: mclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + kmiclk: kmiclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + uartclk: uartclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + wdogclk: wdogclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* FIXME: this actually hangs off the PLL clocks */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + flash0@40000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x40000000 0x04000000>; + bank-width = <4>; + }; + + flash1@44000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x44000000 0x04000000>; + bank-width = <4>; + }; + + /* SMSC 9118 ethernet with PHY and EEPROM */ + ethernet: ethernet@4e000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <0x4e000000 0x10000>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&veth>; + vddvario-supply = <&veth>; + interrupt-parent = <&intc>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb: usb@4f000000 { + compatible = "nxp,usb-isp1761"; + reg = <0x4f000000 0x20000>; + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + port1-otg; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-pba8-soc", "simple-bus"; + regmap = <&syscon>; + ranges; + + syscon: syscon@10000000 { + compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd"; + reg = <0x10000000 0x1000>; + + led@08.0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@08.1 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@08.2 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@08.3 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + default-state = "off"; + }; + led@08.4 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + default-state = "off"; + }; + led@08.5 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + default-state = "off"; + }; + led@08.6 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@08.7 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + oscclk0: osc0@0c { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x0C>; + clocks = <&xtal24mhz>; + }; + oscclk1: osc1@10 { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x10>; + clocks = <&xtal24mhz>; + }; + oscclk2: osc2@14 { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x14>; + clocks = <&xtal24mhz>; + }; + oscclk3: osc3@18 { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x18>; + clocks = <&xtal24mhz>; + }; + oscclk4: osc4@1c { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x1c>; + clocks = <&xtal24mhz>; + }; + }; + + sp810_syscon0: sysctl@10001000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x10001000 0x1000>; + clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclk0", + "timerclk1", + "timerclk2", + "timerclk3"; + assigned-clocks = <&sp810_syscon0 0>, + <&sp810_syscon0 1>, + <&sp810_syscon0 2>, + <&sp810_syscon0 3>; + assigned-clock-parents = <&timclk>, + <&timclk>, + <&timclk>, + <&timclk>; + }; + + i2c: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + serial0: serial@10009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x10009000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; + }; + + serial1: serial@1000a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000a000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; + }; + + serial2: serial@1000b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000b000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + }; + + ssp: ssp@1000d000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1000d000 0x1000>; + clocks = <&sspclk>, <&pclk>; + clock-names = "SSPCLK", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + }; + + wdog0: watchdog@1000f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x1000f000 0x1000>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdogclk", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + wdog1: watchdog@10010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x10010000 0x1000>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdogclk", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer01: timer@10011000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10011000 0x1000>; + clocks = <&sp810_syscon0 0>, + <&sp810_syscon0 1>, + <&pclk>; + clock-names = "timerclk0", + "timerclk1", + "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer23: timer@10012000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10012000 0x1000>; + clocks = <&sp810_syscon0 2>, + <&sp810_syscon0 3>, + <&pclk>; + clock-names = "timerclk2", + "timerclk3", + "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + arm,sp804-has-irq = <1>; + }; + + gpio0: gpio@10013000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10013000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpio1: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + gpio2: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* DVI serial bus control is at 10016000 */ + + rtc: rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer45: timer@10018000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10018000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timerclk4", "timerclk5", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer67: timer@10019000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10019000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timerclk6", "timerclk7", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; + }; + + sp810_syscon1: sysctl@1001a000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x1001a000 0x1000>; + clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclk4", + "timerclk5", + "timerclk6", + "timerclk7"; + assigned-clocks = <&sp810_syscon1 0>, + <&sp810_syscon1 1>, + <&sp810_syscon1 2>, + <&sp810_syscon1 3>; + assigned-clock-parents = <&timclk>, + <&timclk>, + <&timclk>, + <&timclk>; + }; + + /* Primary GIC PL390 interrupt controller in the test chip */ + intc: interrupt-controller@1e000000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000000 0x100>; + }; + }; + + + /* These peripherals are inside the FPGA */ + fpga { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aaci: aaci@10004000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x10004000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + }; + + mmc: mmcsd@10005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x10005000 0x1000>; + + /* Due to frequent FIFO overruns, use just 500 kHz */ + max-frequency = <500000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + clocks = <&mclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + vmmc-supply = <&vmmc>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>; + }; + + kmi0: kmi@10006000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10006000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + kmi1: kmi@10007000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10007000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + }; + + serial3: serial@1000c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000c000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + interrupt-parent = <&intc>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + /* These peripherals are inside the NEC ISSP */ + issp { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + clcd: clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "combined"; + clocks = <&oscclk4>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + + port { + clcd_pads: endpoint { + remote-endpoint = <&clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + clcd_panel: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + /* Standard 640x480 VGA timings */ + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <33>; + vfront-porch = <10>; + vsync-len = <2>; + }; + }; + }; + }; +}; +