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[213.113.122.145]) by smtp.gmail.com with ESMTPSA id rp10sm1057045lbb.13.2016.01.27.14.24.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 27 Jan 2016 14:24:03 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Russell King Subject: [PATCH 1/2] ARM: l2x0: add three special L210 aux control flags Date: Wed, 27 Jan 2016 23:23:57 +0100 Message-Id: <1453933437-6666-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160127_142429_518988_111AC304 X-CRM114-Status: GOOD ( 14.32 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:4010:c04:0:0:0:22f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linus Walleij MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org This adds support for setting the flag bits "wrap access disable", "write allocate override" and "exclusive abort disable" to the L210 variant from the device tree. The "write allocate override" bit was used on the Nomadik and necessary to properly make use of the L210 cache on that machine without sporadic crashes. I took this oppportunity to add all three flags so we avoid excess patching for each one. Cc: Russell King Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/l2c2x0.txt | 10 ++++++++++ arch/arm/mm/cache-l2x0.c | 18 ++++++++++++++++++ 2 files changed, 28 insertions(+) -- 2.4.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.txt b/Documentation/devicetree/bindings/arm/l2c2x0.txt index fe0398c5c77b..975d1ae304d4 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.txt +++ b/Documentation/devicetree/bindings/arm/l2c2x0.txt @@ -74,6 +74,16 @@ Optional properties: or "write through no write allocate" (for writes). On systems where this may cause DMA buffer corruption, this property must be specified to indicate that such transforms are precluded. +- arm,wrap-access-disable : (L210 only) if this flag is set, wrap accesses + requested on slave ports are converted to linear acesses on master ports. +- arm,write-allocate-override : (L210 only) normally the L210 will use HPROT + attributes, setting this bit overrides that behaviour and cause the cache + to make all write-through and write-back accesses into read-write-allocate + accesses. +- arm,exclusive-abort-disable : (L210 only) normally the cache controller sends + an ERROR response back to exclusive access in a cacheable, shared memory + region with the shared override bit set, but setting this flag disables the + abort generation and the access is instead treated as cacheable, non-shared. - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310). - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310). - arm,outer-sync-disable : disable the outer sync operation on the L2 cache. diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 9f9d54271aad..301c3c2dc09f 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1076,6 +1076,24 @@ static void __init l2x0_of_parse(const struct device_node *np, val |= L2C_AUX_CTRL_SHARED_OVERRIDE; } + /* L210-specific aux control flags */ + if (of_device_is_compatible(np, "arm,l210-cache")) { + if (of_property_read_bool(np, "arm,wrap-access-disable")) { + mask &= ~L210_AUX_CTRL_WRAP_DISABLE; + val |= L210_AUX_CTRL_WRAP_DISABLE; + } + + if (of_property_read_bool(np, "arm,write-allocate-override")) { + mask &= ~L210_AUX_CTRL_WA_OVERRIDE; + val |= L210_AUX_CTRL_WA_OVERRIDE; + } + + if (of_property_read_bool(np, "arm,exclusive-abort-disable")) { + mask &= ~L210_AUX_CTRL_EXCLUSIVE_ABORT; + val |= L210_AUX_CTRL_EXCLUSIVE_ABORT; + } + } + ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K); if (ret) return;