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[80.99.35.196]) by smtp.gmail.com with ESMTPSA id w8sm22868636wjx.21.2015.12.30.12.05.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Dec 2015 12:05:22 -0800 (PST) From: Linus Walleij To: arm@kernel.org Subject: [PATCH] ARM: realview: set up cache correctly on the PB11MPCore Date: Wed, 30 Dec 2015 21:05:09 +0100 Message-Id: <1451505909-3820-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151230_120547_807466_65A97F72 X-CRM114-Status: GOOD ( 13.94 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:400c:c09:0:0:0:236 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linus Walleij , Russell King , Arnd Bergmann , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The L2 cache comes up in a "safe mode" on the PB11MPCore, as it has several issues. This sets it up properly with the right size and associativity, also requiring the outer sync to be disabled for the machine to boot properly. Cc: Russell King Cc: Arnd Bergmann Signed-off-by: Linus Walleij --- ARM SoC folks: Russell has merged the outer cache sync disable patch so it would be nice if you'd merge this directly on top of the branch holding the PB11MPCore device tree, so that the cache is feature complete for v4.5. --- arch/arm/boot/dts/arm-realview-pb11mp.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.4.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 28bd5aea285f..3d9b1b0f4ffc 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -99,6 +99,19 @@ <0 31 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s), probably for safety + * since th outer sync operation can cause the + * cache to hang unless disabled. + */ + cache-size = <1048576>; // 1MB + cache-sets = <4096>; + cache-line-size = <32>; + arm,shared-override; + arm,parity-enable; + arm,outer-sync-disable; }; scu@1f000000 {