From patchwork Tue Dec 22 08:08:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 58827 Delivered-To: patch@linaro.org Received: by 10.112.89.199 with SMTP id bq7csp3087278lbb; Tue, 22 Dec 2015 00:14:08 -0800 (PST) X-Received: by 10.66.216.7 with SMTP id om7mr33505494pac.90.1450772048528; Tue, 22 Dec 2015 00:14:08 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id hp4si1695091pad.113.2015.12.22.00.14.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Dec 2015 00:14:08 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1aBI4C-0003b8-Hw; Tue, 22 Dec 2015 08:13:08 +0000 Received: from szxga03-in.huawei.com ([119.145.14.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1aBI47-0002vK-A9 for linux-arm-kernel@lists.infradead.org; Tue, 22 Dec 2015 08:13:05 +0000 Received: from 172.24.1.51 (EHLO szxeml431-hub.china.huawei.com) ([172.24.1.51]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BTD72691; Tue, 22 Dec 2015 16:09:04 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml431-hub.china.huawei.com (10.82.67.208) with Microsoft SMTP Server id 14.3.235.1; Tue, 22 Dec 2015 16:08:55 +0800 From: Shannon Zhao To: , , Subject: [PATCH v8 20/20] KVM: ARM64: Add a new kvm ARM PMU device Date: Tue, 22 Dec 2015 16:08:15 +0800 Message-ID: <1450771695-11948-21-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1450771695-11948-1-git-send-email-zhaoshenglong@huawei.com> References: <1450771695-11948-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0202.56790520.032C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: ebc7bbffdba2b4cd67188e945e3968d7 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151222_001303_992153_B09D0A8A X-CRM114-Status: GOOD ( 20.86 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [119.145.14.66 listed in list.dnswl.org] -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [119.145.14.66 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, shannon.zhao@linaro.org, zhaoshenglong@huawei.com, linux-arm-kernel@lists.infradead.org, cov@codeaurora.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement the kvm_device_ops for it. Signed-off-by: Shannon Zhao --- Documentation/virtual/kvm/devices/arm-pmu.txt | 24 +++++ arch/arm64/include/uapi/asm/kvm.h | 4 + include/linux/kvm_host.h | 1 + include/uapi/linux/kvm.h | 2 + virt/kvm/arm/pmu.c | 128 ++++++++++++++++++++++++++ virt/kvm/kvm_main.c | 4 + 6 files changed, 163 insertions(+) create mode 100644 Documentation/virtual/kvm/devices/arm-pmu.txt -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/Documentation/virtual/kvm/devices/arm-pmu.txt b/Documentation/virtual/kvm/devices/arm-pmu.txt new file mode 100644 index 0000000..dda864e --- /dev/null +++ b/Documentation/virtual/kvm/devices/arm-pmu.txt @@ -0,0 +1,24 @@ +ARM Virtual Performance Monitor Unit (vPMU) +=========================================== + +Device types supported: + KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3 + +Instantiate one PMU instance for per VCPU through this API. + +Groups: + KVM_DEV_ARM_PMU_GRP_IRQ + Attributes: + The attr field of kvm_device_attr encodes one value: + bits: | 63 .... 32 | 31 .... 0 | + values: | reserved | vcpu_index | + A value describing the PMU overflow interrupt number for the specified + vcpu_index vcpu. This interrupt could be a PPI or SPI, but for one VM the + interrupt type must be same for each vcpu. As a PPI, the interrupt number is + same for all vcpus, while as a SPI it must be different for each vcpu. + + Errors: + -ENXIO: Unsupported attribute group + -EBUSY: The PMU overflow interrupt is already set + -ENODEV: Getting the PMU overflow interrupt number while it's not set + -EINVAL: Invalid vcpu_index or PMU overflow interrupt number supplied diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 2d4ca4b..cbb9022 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -204,6 +204,10 @@ struct kvm_arch_memory_slot { #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 +/* Device Control API: ARM PMU */ +#define KVM_DEV_ARM_PMU_GRP_IRQ 0 +#define KVM_DEV_ARM_PMU_CPUID_MASK 0xffffffffULL + /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_TYPE_SHIFT 24 #define KVM_ARM_IRQ_TYPE_MASK 0xff diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index c923350..608dea6 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -1161,6 +1161,7 @@ extern struct kvm_device_ops kvm_mpic_ops; extern struct kvm_device_ops kvm_xics_ops; extern struct kvm_device_ops kvm_arm_vgic_v2_ops; extern struct kvm_device_ops kvm_arm_vgic_v3_ops; +extern struct kvm_device_ops kvm_arm_pmu_ops; #ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 03f3618..4ba6fdd 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1032,6 +1032,8 @@ enum kvm_device_type { #define KVM_DEV_TYPE_FLIC KVM_DEV_TYPE_FLIC KVM_DEV_TYPE_ARM_VGIC_V3, #define KVM_DEV_TYPE_ARM_VGIC_V3 KVM_DEV_TYPE_ARM_VGIC_V3 + KVM_DEV_TYPE_ARM_PMU_V3, +#define KVM_DEV_TYPE_ARM_PMU_V3 KVM_DEV_TYPE_ARM_PMU_V3 KVM_DEV_TYPE_MAX, }; diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 3ec3cdd..5518308 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -374,3 +375,130 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, pmc->perf_event = event; } + +static inline bool kvm_arm_pmu_initialized(struct kvm_vcpu *vcpu) +{ + return vcpu->arch.pmu.irq_num != -1; +} + +static int kvm_arm_pmu_irq_access(struct kvm *kvm, struct kvm_device_attr *attr, + int *irq, bool is_set) +{ + int cpuid; + struct kvm_vcpu *vcpu; + struct kvm_pmu *pmu; + + cpuid = attr->attr & KVM_DEV_ARM_PMU_CPUID_MASK; + if (cpuid >= atomic_read(&kvm->online_vcpus)) + return -EINVAL; + + vcpu = kvm_get_vcpu(kvm, cpuid); + if (!vcpu) + return -EINVAL; + + pmu = &vcpu->arch.pmu; + if (!is_set) { + if (!kvm_arm_pmu_initialized(vcpu)) + return -ENODEV; + + *irq = pmu->irq_num; + } else { + if (kvm_arm_pmu_initialized(vcpu)) + return -EBUSY; + + kvm_debug("Set kvm ARM PMU irq: %d\n", *irq); + pmu->irq_num = *irq; + } + + return 0; +} + +static int kvm_arm_pmu_create(struct kvm_device *dev, u32 type) +{ + int i; + struct kvm_vcpu *vcpu; + struct kvm *kvm = dev->kvm; + + kvm_for_each_vcpu(i, vcpu, kvm) { + struct kvm_pmu *pmu = &vcpu->arch.pmu; + + memset(pmu, 0, sizeof(*pmu)); + kvm_pmu_vcpu_reset(vcpu); + pmu->irq_num = -1; + } + + return 0; +} + +static void kvm_arm_pmu_destroy(struct kvm_device *dev) +{ + kfree(dev); +} + +static int kvm_arm_pmu_set_attr(struct kvm_device *dev, + struct kvm_device_attr *attr) +{ + switch (attr->group) { + case KVM_DEV_ARM_PMU_GRP_IRQ: { + int __user *uaddr = (int __user *)(long)attr->addr; + int reg; + + if (get_user(reg, uaddr)) + return -EFAULT; + + /* + * The PMU overflow interrupt could be a PPI or SPI, but for one + * VM the interrupt type must be same for each vcpu. As a PPI, + * the interrupt number is same for all vcpus, while as a SPI it + * must be different for each vcpu. + */ + if (reg < VGIC_NR_SGIS || reg >= dev->kvm->arch.vgic.nr_irqs) + return -EINVAL; + + return kvm_arm_pmu_irq_access(dev->kvm, attr, ®, true); + } + } + + return -ENXIO; +} + +static int kvm_arm_pmu_get_attr(struct kvm_device *dev, + struct kvm_device_attr *attr) +{ + int ret; + + switch (attr->group) { + case KVM_DEV_ARM_PMU_GRP_IRQ: { + int __user *uaddr = (int __user *)(long)attr->addr; + int reg = -1; + + + ret = kvm_arm_pmu_irq_access(dev->kvm, attr, ®, false); + if (ret) + return ret; + return put_user(reg, uaddr); + } + } + + return -ENXIO; +} + +static int kvm_arm_pmu_has_attr(struct kvm_device *dev, + struct kvm_device_attr *attr) +{ + switch (attr->group) { + case KVM_DEV_ARM_PMU_GRP_IRQ: + return 0; + } + + return -ENXIO; +} + +struct kvm_device_ops kvm_arm_pmu_ops = { + .name = "kvm-arm-pmu", + .create = kvm_arm_pmu_create, + .destroy = kvm_arm_pmu_destroy, + .set_attr = kvm_arm_pmu_set_attr, + .get_attr = kvm_arm_pmu_get_attr, + .has_attr = kvm_arm_pmu_has_attr, +}; diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index 484079e..81a42cc 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -2647,6 +2647,10 @@ static struct kvm_device_ops *kvm_device_ops_table[KVM_DEV_TYPE_MAX] = { #ifdef CONFIG_KVM_XICS [KVM_DEV_TYPE_XICS] = &kvm_xics_ops, #endif + +#ifdef CONFIG_KVM_ARM_PMU + [KVM_DEV_TYPE_ARM_PMU_V3] = &kvm_arm_pmu_ops, +#endif }; int kvm_register_device_ops(struct kvm_device_ops *ops, u32 type)