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[213.113.116.41]) by smtp.gmail.com with ESMTPSA id j204sm5459769lfd.16.2015.12.14.06.32.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Dec 2015 06:33:00 -0800 (PST) From: Linus Walleij To: Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth Subject: [PATCH 0/2 v3] ARM: mvebu: kirkwood: add PogoPlug series 4 device tree Date: Mon, 14 Dec 2015 15:32:55 +0100 Message-Id: <1450103575-10066-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151214_063323_661565_D9F2E6CF X-CRM114-Status: GOOD ( 16.75 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:4010:c07:0:0:0:232 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linus Walleij , Kevin Mihelich , Moonman , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org This adds a device tree for the CloudEngines PogoPlug series 4 NAS device. Inspired by out-of-tree boardfiles from ArchLinux by Kevin Mihelich. Cc: Moonman Cc: Kevin Mihelich Signed-off-by: Linus Walleij --- ChangeLog v2->v3: - Drop current-speed = <115200> from the uart ChangeLog v1->v2: - Use - Specify default baud rate etc differently - Rename LEDs "pogoplugv4*" - Skip registering i2c0 as there is nothing on it --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts | 178 +++++++++++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts -- 2.4.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 30bbc3746130..2d9f475a9ceb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -206,6 +206,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-openrd-client.dtb \ kirkwood-openrd-ultimate.dtb \ kirkwood-pogo_e02.dtb \ + kirkwood-pogoplug-series-4.dtb \ kirkwood-rd88f6192.dtb \ kirkwood-rd88f6281-z0.dtb \ kirkwood-rd88f6281-a.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts new file mode 100644 index 000000000000..1db6f2c506cc --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts @@ -0,0 +1,178 @@ +/* + * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 + * inspired by the board files made by Kevin Mihelich for ArchLinux, + * and their DTS file. + * + * Copyright (C) 2015 Linus Walleij + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6192.dtsi" +#include + +/ { + model = "Cloud Engines PogoPlug Series 4"; + compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", + "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + chosen { + stdout-path = "uart0:115200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_button_eject>; + pinctrl-names = "default"; + + button@1 { + debounce_interval = <50>; + wakeup-source; + linux,code = ; + label = "Eject Button"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_green &pmx_led_red>; + pinctrl-names = "default"; + + health { + label = "pogoplugv4:green:health"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + fault { + label = "pogoplugv4:red:fault"; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl { + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp21"; + marvell,function = "sata0"; + }; + + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp20"; + marvell,function = "sata1"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + pmx_sdio_wp: pmx-sdio-wp { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_button_eject: pmx-button-eject { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_green: pmx-led-green { + marvell,pins = "mpp22"; + marvell,function = "gpio"; + }; + + pmx_led_red: pmx-led-red { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; +}; + +&uart0 { + status = "okay"; +}; + +/* + * This PCIE controller has a USB 3.0 XHCI controller at 1,0 + */ +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&sata { + status = "okay"; + pinctrl-0 = <&pmx_sata0 &pmx_sata1>; + pinctrl-names = "default"; + nr-ports = <1>; +}; + +&sdio { + status = "okay"; + pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; + pinctrl-names = "default"; + cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; +}; + +&nand { + /* 128 MiB of NAND flash */ + chip-delay = <40>; + status = "okay"; + partitions { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x200000>; + read-only; + }; + + partition@200000 { + label = "uImage"; + reg = <0x00200000 0x300000>; + }; + + partition@500000 { + label = "uImage2"; + reg = <0x00500000 0x300000>; + }; + + partition@800000 { + label = "failsafe"; + reg = <0x00800000 0x800000>; + }; + + partition@1000000 { + label = "root"; + reg = <0x01000000 0x7000000>; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +};