From patchwork Thu Dec 3 06:11:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 57598 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp3313380lbb; Wed, 2 Dec 2015 22:15:57 -0800 (PST) X-Received: by 10.98.72.18 with SMTP id v18mr10737411pfa.68.1449123357364; Wed, 02 Dec 2015 22:15:57 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id sy8si9850852pac.67.2015.12.02.22.15.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Dec 2015 22:15:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4N9s-0008A3-TY; Thu, 03 Dec 2015 06:14:24 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4N9J-0007bj-La for linux-arm-kernel@lists.infradead.org; Thu, 03 Dec 2015 06:13:53 +0000 Received: from 172.24.1.48 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.48]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DAC88334; Thu, 03 Dec 2015 14:12:28 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Thu, 3 Dec 2015 14:12:21 +0800 From: Shannon Zhao To: , , Subject: [PATCH v5 08/21] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Date: Thu, 3 Dec 2015 14:11:18 +0800 Message-ID: <1449123091-20252-9-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> References: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.565FDD4C.00F5, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2a71a9a929717d795a7985b2ce89d729 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151202_221350_449476_EAE9315B X-CRM114-Status: GOOD ( 12.21 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or reset_unknown_cp15 for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER register. When writing to PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event for the selected event type. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b0a8d88..6967a49 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -473,6 +473,17 @@ static void reset_pmceid(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) vcpu_sys_reg(vcpu, r->reg) = pmceid; } +static bool pmu_counter_idx_valid(u64 pmcr, u64 idx) +{ + u64 val; + + val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK; + if (idx >= val && idx != ARMV8_COUNTER_MASK) + return false; + + return true; +} + /* PMU registers accessor. */ static bool access_pmu_regs(struct kvm_vcpu *vcpu, const struct sys_reg_params *p, @@ -482,6 +493,20 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case PMXEVTYPER_EL0: { + u64 idx = vcpu_sys_reg(vcpu, PMSELR_EL0) + & ARMV8_COUNTER_MASK; + + if (!pmu_counter_idx_valid(vcpu_sys_reg(vcpu, PMCR_EL0), + idx)) + break; + + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_set_counter_event_type(vcpu, val, idx); + vcpu_sys_reg(vcpu, PMXEVTYPER_EL0) = val; + vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + idx) = val; + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -726,7 +751,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { trap_raz_wi }, /* PMXEVTYPER_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMXEVTYPER_EL0 }, /* PMXEVCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010), trap_raz_wi }, @@ -942,6 +967,20 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case c9_PMXEVTYPER: { + u32 idx = vcpu_cp15(vcpu, c9_PMSELR) + & ARMV8_COUNTER_MASK; + + if (!pmu_counter_idx_valid(vcpu_sys_reg(vcpu, c9_PMCR), + idx)) + break; + + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_set_counter_event_type(vcpu, val, idx); + vcpu_cp15(vcpu, c9_PMXEVTYPER) = val; + vcpu_cp15(vcpu, c14_PMEVTYPER0 + idx) = val; + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -1015,7 +1054,8 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs, NULL, c9_PMCEID1 }, { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_cp15_regs, + NULL, c9_PMXEVTYPER }, { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },