From patchwork Thu Dec 3 06:11:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 57610 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp3316284lbb; Wed, 2 Dec 2015 22:24:33 -0800 (PST) X-Received: by 10.98.16.7 with SMTP id y7mr10736161pfi.25.1449123873255; Wed, 02 Dec 2015 22:24:33 -0800 (PST) Return-Path: Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id c5si9905335pas.41.2015.12.02.22.24.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Dec 2015 22:24:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4NIC-0000vP-JU; Thu, 03 Dec 2015 06:23:00 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4NCc-0002V1-Kl for linux-arm-kernel@lists.infradead.org; Thu, 03 Dec 2015 06:17:56 +0000 Received: from 172.24.1.51 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.51]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CXG85933; Thu, 03 Dec 2015 14:12:38 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Thu, 3 Dec 2015 14:12:31 +0800 From: Shannon Zhao To: , , Subject: [PATCH v5 17/21] KVM: ARM64: Add helper to handle PMCR register bits Date: Thu, 3 Dec 2015 14:11:27 +0800 Message-ID: <1449123091-20252-18-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> References: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.565FDD56.00BC, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 5a1fadf43d947930c08bf097db2819c0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151202_221716_900099_D8556531 X-CRM114-Status: GOOD ( 13.90 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [119.145.14.65 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [119.145.14.65 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao According to ARMv8 spec, when writing 1 to PMCR.E, all counters are enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are disabled. When writing 1 to PMCR.P, reset all event counters, not including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to zero. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 2 ++ include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 9320277..405cf70 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -578,6 +578,7 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, val &= ~ARMV8_PMCR_MASK; val |= *vcpu_reg(vcpu, p->Rt) & ARMV8_PMCR_MASK; vcpu_sys_reg(vcpu, r->reg) = val; + kvm_pmu_handle_pmcr(vcpu, val); break; } case PMCEID0_EL0: @@ -1219,6 +1220,7 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, val &= ~ARMV8_PMCR_MASK; val |= *vcpu_reg(vcpu, p->Rt) & ARMV8_PMCR_MASK; vcpu_cp15(vcpu, r->reg) = val; + kvm_pmu_handle_pmcr(vcpu, val); break; } case c9_PMCEID0: diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index a54c391..212a3de 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -47,6 +47,7 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx); +void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val); #else unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx) { @@ -59,6 +60,7 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx) {} +void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val) {} #endif #endif diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index d133909..b81e35e 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -140,6 +140,57 @@ static unsigned long kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) } /** + * kvm_pmu_handle_pmcr - handle PMCR register + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMCR register + */ +void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u32 val) +{ + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc; + u32 enable; + int i; + + if (val & ARMV8_PMCR_E) { + if (!vcpu_mode_is_32bit(vcpu)) + enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0); + else + enable = vcpu_cp15(vcpu, c9_PMCNTENSET); + + kvm_pmu_enable_counter(vcpu, enable, true); + } else { + kvm_pmu_disable_counter(vcpu, 0xffffffffUL); + } + + if (val & ARMV8_PMCR_C) { + pmc = &pmu->pmc[ARMV8_MAX_COUNTERS - 1]; + if (pmc->perf_event) + local64_set(&pmc->perf_event->count, 0); + if (!vcpu_mode_is_32bit(vcpu)) + vcpu_sys_reg(vcpu, PMCCNTR_EL0) = 0; + else + vcpu_cp15(vcpu, c9_PMCCNTR) = 0; + } + + if (val & ARMV8_PMCR_P) { + for (i = 0; i < ARMV8_MAX_COUNTERS - 1; i++) { + pmc = &pmu->pmc[i]; + if (pmc->perf_event) + local64_set(&pmc->perf_event->count, 0); + if (!vcpu_mode_is_32bit(vcpu)) + vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = 0; + else + vcpu_cp15(vcpu, c14_PMEVCNTR0 + i) = 0; + } + } + + if (val & ARMV8_PMCR_LC) { + pmc = &pmu->pmc[ARMV8_MAX_COUNTERS - 1]; + pmc->bitmask = 0xffffffffffffffffUL; + } +} + +/** * kvm_pmu_overflow_clear - clear PMU overflow interrupt * @vcpu: The vcpu pointer * @val: the value guest writes to PMOVSCLR register