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[2001:1868:205::9]) by mx.google.com with ESMTPS id w74si9903272pfi.93.2015.12.02.22.25.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Dec 2015 22:25:08 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4NIn-0001VV-R5; Thu, 03 Dec 2015 06:23:37 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1a4NCd-0002V9-Nb for linux-arm-kernel@lists.infradead.org; Thu, 03 Dec 2015 06:18:11 +0000 Received: from 172.24.1.51 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.51]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CXG85935; Thu, 03 Dec 2015 14:12:38 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Thu, 3 Dec 2015 14:12:29 +0800 From: Shannon Zhao To: , , Subject: [PATCH v5 15/21] KVM: ARM64: Add reset and access handlers for PMSWINC register Date: Thu, 3 Dec 2015 14:11:25 +0800 Message-ID: <1449123091-20252-16-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> References: <1449123091-20252-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.565FDD57.0033, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d658d5cf1a90a087e6be213451d80349 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151202_221719_825870_F066B761 X-CRM114-Status: GOOD ( 16.77 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [119.145.14.65 listed in wl.mailspike.net] -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [119.145.14.65 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, hangaohuai@huawei.com, kvm@vger.kernel.org, will.deacon@arm.com, peter.huangpeng@huawei.com, cov@codeaurora.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, linux-arm-kernel@lists.infradead.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org From: Shannon Zhao Add access handler which emulates writing and reading PMSWINC register and add support for creating software increment event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 18 +++++++++++++++++- include/kvm/arm_pmu.h | 2 ++ virt/kvm/arm/pmu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+), 1 deletion(-) -- 2.0.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index eb4fcf9..12f4806 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -567,6 +567,11 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, kvm_pmu_overflow_clear(vcpu, *vcpu_reg(vcpu, p->Rt)); break; } + case PMSWINC_EL0: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_software_increment(vcpu, val); + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -602,6 +607,8 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, *vcpu_reg(vcpu, p->Rt) = val; break; } + case PMSWINC_EL0: + return read_zero(vcpu, p); case PMCR_EL0: { /* PMCR.P & PMCR.C are RAZ */ val = vcpu_sys_reg(vcpu, r->reg) @@ -814,7 +821,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMOVSCLR_EL0 }, /* PMSWINC_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMSWINC_EL0 }, /* PMSELR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101), access_pmu_regs, reset_unknown, PMSELR_EL0 }, @@ -1119,6 +1126,11 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, kvm_pmu_overflow_clear(vcpu, *vcpu_reg(vcpu, p->Rt)); break; } + case c9_PMSWINC: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_software_increment(vcpu, val); + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -1154,6 +1166,8 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, *vcpu_reg(vcpu, p->Rt) = val; break; } + case c9_PMSWINC: + return read_zero(vcpu, p); case c9_PMCR: { /* PMCR.P & PMCR.C are RAZ */ val = vcpu_cp15(vcpu, r->reg) @@ -1206,6 +1220,8 @@ static const struct sys_reg_desc cp15_regs[] = { NULL, c9_PMCNTENCLR }, { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs, NULL, c9_PMOVSCLR }, + { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmu_cp15_regs, + NULL, c9_PMSWINC }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs, NULL, c9_PMSELR }, { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 4f3154c..a54c391 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -44,6 +44,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable); void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val); +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx); #else @@ -55,6 +56,7 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool all_enable) {} void kvm_pmu_overflow_clear(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) {} +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx) {} #endif diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 296b4ad..d133909 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -206,6 +206,46 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u32 val) } /** + * kvm_pmu_software_increment - do software increment + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMSWINC register + */ +void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) +{ + int i; + u32 type, enable, reg; + + if (val == 0) + return; + + for (i = 0; i < ARMV8_MAX_COUNTERS; i++) { + if (!((val >> i) & 0x1)) + continue; + if (!vcpu_mode_is_32bit(vcpu)) { + type = vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i) + & ARMV8_EVTYPE_EVENT; + enable = vcpu_sys_reg(vcpu, PMCNTENSET_EL0); + if ((type == 0) && ((enable >> i) & 0x1)) { + vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i)++; + reg = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i); + if ((reg & 0xFFFFFFFF) == 0) + kvm_pmu_overflow_set(vcpu, 1 >> i); + } + } else { + type = vcpu_cp15(vcpu, c14_PMEVTYPER0 + i) + & ARMV8_EVTYPE_EVENT; + enable = vcpu_cp15(vcpu, c9_PMCNTENSET); + if ((type == 0) && ((enable >> i) & 0x1)) { + vcpu_cp15(vcpu, c14_PMEVCNTR0 + i)++; + reg = vcpu_cp15(vcpu, c14_PMEVCNTR0 + i); + if ((reg & 0xFFFFFFFF) == 0) + kvm_pmu_overflow_set(vcpu, 1 >> i); + } + } + } +} + +/** * kvm_pmu_set_counter_event_type - set selected counter to monitor some event * @vcpu: The vcpu pointer * @data: The data guest writes to PMXEVTYPER_EL0 @@ -228,6 +268,10 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, kvm_pmu_stop_counter(pmc); eventsel = data & ARMV8_EVTYPE_EVENT; + /* For software increment event it does't need to create perf event */ + if (eventsel == 0) + return; + memset(&attr, 0, sizeof(struct perf_event_attr)); attr.type = PERF_TYPE_RAW; attr.size = sizeof(attr);