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[2001:1868:205::9]) by mx.google.com with ESMTPS id xe6si10404110pab.190.2015.10.30.04.48.58 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Oct 2015 04:48:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dkim=neutral (body hash did not verify) header.i=@linaro_org.20150623.gappssmtp.com Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zs89R-0004cS-5b; Fri, 30 Oct 2015 11:47:21 +0000 Received: from mail-wm0-x231.google.com ([2a00:1450:400c:c09::231]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zs89N-0004Zh-V9 for linux-arm-kernel@lists.infradead.org; Fri, 30 Oct 2015 11:47:18 +0000 Received: by wmll128 with SMTP id l128so10107148wml.0 for ; Fri, 30 Oct 2015 04:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro_org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=rgoubbR/7ljm00I8TBPr9ND5EeLNd5G5de0aw89BIOk=; b=QEvbuUd+mLCuHsMWJoBJPrl29h9t0ZDkEYDi70WuFaxrV+csrC46HUNvZPYssxxbWL WUhTdg5Re/2NRek7WYfLH6ExXo9v+Sq3NaksdSn1+UCO44aQQBhEyay5y9kP+r5NGDbX d4xbXsFAEITOU3UFV2yFDCOvFyTA2/D+321Wv/+E3GE28oTF3WFXrbnWC13/Ktft1ewQ rjK8wf212EUQ4SnECMXOsR5q0GVPCS5At+pMsReS3Av91lu4EHVIXVcAqGW1YaT93EtI oSHj1tQ9iGYnHcVGHdlNkmDH+h54FxXl+hprjdP9HAt7reAwLlFBnYIEEdwSlsY7mYkT 0hZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=rgoubbR/7ljm00I8TBPr9ND5EeLNd5G5de0aw89BIOk=; b=eV4sg/irI88xUwhVx89ZGQlXPpC3Fna6by1aMAfs1rS4xhLC49Zh8PQT0ANmHnao01 cpOJKKMsGmP1C8xhRGzHEuYnJreSbcqwPketj6vdfxqnLXj+wsBXCQUpSJ8tQtHy5TWK 8DbgZviKAZ11NjRzRHx2Zz4gyjnRBNyBO8MgWynSwakEzJeY8n938Exs843Sn5db9wGV njLkk/U+WYesY30HtEEgRi50kda9kXLnff7iywVWjr1JLa/5qDfXlAs3z+gkrxFdRJHm sBgtq9i4KRS5DkfIpaGCF6FF3gvAQF+2Y4z06GZ5/7nR51V4uKHkSo3MtMZo4q4le3X5 hNJA== X-Gm-Message-State: ALoCoQkm7TDKRHb3yJyBF49mAmW9s3YJNhpJg2IStTtnW3tziLI35ou9vznt/ACp9x1c9JqIZV6q X-Received: by 10.28.22.67 with SMTP id 64mr2799957wmw.61.1446205616142; Fri, 30 Oct 2015 04:46:56 -0700 (PDT) Received: from jessie.localdomain ([2.41.7.188]) by smtp.gmail.com with ESMTPSA id om1sm6705645wjc.2.2015.10.30.04.46.53 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 30 Oct 2015 04:46:55 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux@arm.linux.org.uk Subject: [PATCH] ARM: don't infer VIPT I-cache properties from its reported geometry Date: Fri, 30 Oct 2015 12:46:43 +0100 Message-Id: <1446205603-14285-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.1.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151030_044718_204442_4B5E3DDC X-CRM114-Status: GOOD ( 13.44 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, avanbrunt@nvidia.com, Ard Biesheuvel MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org The cache geometry reported by the CCSIDR system registers is tightly coupled to the instructions to perform cache maintenance by set/way, and the architecture explicitly forbids inferring anything about the actual cache geometry from them: The parameters NumSets, Associativity, and LineSize in these registers define the architecturally visible parameters that are required for the cache maintenance by Set/Way instructions. They are not guaranteed to represent the actual microarchitectural features of a design. You cannot make any inference about the actual sizes of caches based on these parameters. This includes calculating the way size of a VIPT I-cache to decide whether it is free of aliases. So remove the code that implements this for v7 CPUs, and treat all non-PIPT I-caches as aliasing instead. Reported-by: Alex Van Brunt Signed-off-by: Ard Biesheuvel --- arch/arm/kernel/setup.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) -- 2.1.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 20edd349d379..1275135488ee 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -279,7 +279,6 @@ int __pure cpu_architecture(void) static int cpu_has_aliasing_icache(unsigned int arch) { int aliasing_icache; - unsigned int id_reg, num_sets, line_size; /* PIPT caches never alias. */ if (icache_is_pipt()) @@ -288,15 +287,7 @@ static int cpu_has_aliasing_icache(unsigned int arch) /* arch specifies the register format */ switch (arch) { case CPU_ARCH_ARMv7: - asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR" - : /* No output operands */ - : "r" (1)); - isb(); - asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR" - : "=r" (id_reg)); - line_size = 4 << ((id_reg & 0x7) + 2); - num_sets = ((id_reg >> 13) & 0x7fff) + 1; - aliasing_icache = (line_size * num_sets) > PAGE_SIZE; + aliasing_icache = 1; break; case CPU_ARCH_ARMv6: aliasing_icache = read_cpuid_cachetype() & (1 << 11);