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[2001:1868:205::9]) by mx.google.com with ESMTPS id ia9si7559438obb.18.2015.10.15.06.49.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Oct 2015 06:49:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZmitA-0002BS-48; Thu, 15 Oct 2015 13:48:12 +0000 Received: from mail-lb0-f182.google.com ([209.85.217.182]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zmisi-0001pi-Rv for linux-arm-kernel@lists.infradead.org; Thu, 15 Oct 2015 13:47:46 +0000 Received: by lbbwb3 with SMTP id wb3so7200743lbb.1 for ; Thu, 15 Oct 2015 06:47:23 -0700 (PDT) X-Received: by 10.112.151.106 with SMTP id up10mr4651048lbb.106.1444916843074; Thu, 15 Oct 2015 06:47:23 -0700 (PDT) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id ug9sm2056977lbb.22.2015.10.15.06.47.20 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Oct 2015 06:47:22 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Russell King Subject: [PATCH 04/13] irqchip/gic: support RealView variant setup Date: Thu, 15 Oct 2015 15:46:44 +0200 Message-Id: <1444916813-31024-5-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1444916813-31024-1-git-send-email-linus.walleij@linaro.org> References: <1444916813-31024-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151015_064745_207309_2087FC6F X-CRM114-Status: GOOD ( 27.00 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.217.182 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.217.182 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: Mark Rutland , Jason Cooper , Pawel Moll , Marc Zyngier , Linus Walleij , Will Deacon , Thomas Gleixner MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The ARM RealView PB11MPCore reference design has some special bits in a system controller register to set up the GIC in one of three modes: legacy, new with DCC, new without DCC. The register is also used to enable FIQ. Since the platform will not boot unless this register is set up to "new with DCC" mode, we need a special quirk to be compiled-in for the RealView platforms. If we find the right compatible string on the GIC TestChip, we enable this quirk by looking up the system controller and enabling the special bits. We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old boardfile code has the same fix hardcoded, and this is only needed for the attempts to modernize the RealView code using device tree. After fixing this, the PB11MPCore boots with device tree only. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Signed-off-by: Linus Walleij --- Looking for an ACK for this (unless the irqchip maintainers barf at it) so I can take it through the ARM SoC tree. --- drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-realview.c | 39 ++++++++++++++++++++++++++++++++++++++ drivers/irqchip/irq-gic-realview.h | 5 +++++ drivers/irqchip/irq-gic.c | 4 ++++ 4 files changed, 49 insertions(+) create mode 100644 drivers/irqchip/irq-gic-realview.c create mode 100644 drivers/irqchip/irq-gic-realview.h diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index bb3048f00e64..7a7d4182777d 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o +obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o diff --git a/drivers/irqchip/irq-gic-realview.c b/drivers/irqchip/irq-gic-realview.c new file mode 100644 index 000000000000..2e8a4b129f5f --- /dev/null +++ b/drivers/irqchip/irq-gic-realview.c @@ -0,0 +1,39 @@ +/* + * Special GIC quirks for the ARM RealView + * Copyright (C) 2015 Linus Walleij + */ +#include +#include +#include +#include + +#define REALVIEW_SYS_LOCK_OFFSET 0x20 +#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 +#define VERSATILE_LOCK_VAL 0xA05F +#define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24) +#define PLD_INTMODE_LEGACY 0x0 +#define PLD_INTMODE_NEW_DCC BIT(22) +#define PLD_INTMODE_NEW_NO_DCC BIT(23) +#define PLD_INTMODE_FIQ_ENABLE BIT(24) + +void __init realview_gic_init(struct device_node *np) +{ + static struct regmap *map; + + /* The PB11MPCore GIC needs to be configured in the syscon */ + if (of_device_is_compatible(np, "arm,tc11mp-gic")) { + map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon"); + if (!IS_ERR(map)) { + /* new irq mode with no DCC */ + regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, + VERSATILE_LOCK_VAL); + regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1, + PLD_INTMODE_NEW_NO_DCC, + PLD_INTMODE_MASK); + regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000); + pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n"); + } else { + pr_err("TC11MP GIC setup: could not find syscon\n"); + } + } +} diff --git a/drivers/irqchip/irq-gic-realview.h b/drivers/irqchip/irq-gic-realview.h new file mode 100644 index 000000000000..06ebdfc523a8 --- /dev/null +++ b/drivers/irqchip/irq-gic-realview.h @@ -0,0 +1,5 @@ +#ifdef CONFIG_REALVIEW_DT +void realview_gic_init(struct device_node *np); +#else +static void realview_gic_init(struct device_node *np) {} +#endif diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 5376d1cb0a4f..bd021e1e4847 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -50,6 +50,7 @@ #include #include "irq-gic-common.h" +#include "irq-gic-realview.h" union gic_base { void __iomem *common_base; @@ -1158,6 +1159,9 @@ gic_of_init(struct device_node *node, struct device_node *parent) cpu_base = of_iomap(node, 1); WARN(!cpu_base, "unable to map gic cpu registers\n"); + /* Special quirk for ARM RealView */ + realview_gic_init(node); + /* * Disable split EOI/Deactivate if either HYP is not available * or the CPU interface is too small.