From patchwork Wed Oct 7 10:37:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 54576 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f72.google.com (mail-la0-f72.google.com [209.85.215.72]) by patches.linaro.org (Postfix) with ESMTPS id 88B7C22FEF for ; Wed, 7 Oct 2015 10:40:35 +0000 (UTC) Received: by laff3 with SMTP id f3sf5336082laf.0 for ; Wed, 07 Oct 2015 03:40:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :precedence:list-id:list-unsubscribe:list-archive:list-post :list-help:list-subscribe:cc:mime-version:content-type :content-transfer-encoding:sender:errors-to:x-original-sender :x-original-authentication-results:mailing-list; bh=85CvSmpZciqPdHeNOWHlo1u0l287FrYFS57O6Nhti3A=; b=cq48ZKb77cbdEpUihJNLiwT1Lym9QBep0Bt3YJvakWyrhpIlhzDLiz4F7XuLwB9W4B 05Lk1CKoHt6ylHth+86CcHFOtDTji7g2I9lZmlvQRNpll4vAnmrP3Gly/rQ9/pKvKHXV JY2K0TaLSM/HGJzUcN4HiLdz6m3OvYzai/IhA7fdKXlkgxezeOKI2suswXeSDL+EkdYm Q27koHQRIyHKhBQXzsn7NDRtT5gi01//THwGjA7KrrwaYOZEH6hYW7ioBsteMmS0YxJW imQYJBLJjJAEftPLtL6ExSVxFQNBrG/6+jG1StrT23uhR1Uwjrks0E92w53UkU/vfyJx 1GKA== X-Gm-Message-State: ALoCoQmlAPzCrF76ghy4eZ68gVRL2CVaprWE/73NY2yC+xb0TXqVbD5QsLXOp5beTXy57q6O4VyZ X-Received: by 10.112.130.41 with SMTP id ob9mr61555lbb.17.1444214434499; Wed, 07 Oct 2015 03:40:34 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.25.44.12 with SMTP id s12ls49029lfs.90.gmail; Wed, 07 Oct 2015 03:40:34 -0700 (PDT) X-Received: by 10.25.170.206 with SMTP id t197mr118690lfe.64.1444214434199; Wed, 07 Oct 2015 03:40:34 -0700 (PDT) Received: from mail-lb0-f178.google.com (mail-lb0-f178.google.com. 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[2001:1868:205::9]) by mx.google.com with ESMTPS id n4si3039226wia.64.2015.10.07.03.40.29 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Oct 2015 03:40:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zjm6l-0003xX-08; Wed, 07 Oct 2015 10:38:03 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zjm6i-0003lA-EN for linux-arm-kernel@lists.infradead.org; Wed, 07 Oct 2015 10:38:01 +0000 Received: from edgewater-inn.cambridge.arm.com (edgewater-inn.cambridge.arm.com [10.1.203.122]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id t97AbaWr019990; Wed, 7 Oct 2015 11:37:36 +0100 (BST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id B2B2D1AE102E; Wed, 7 Oct 2015 11:37:37 +0100 (BST) From: Will Deacon To: catalin-marinas@arm.com Subject: [PATCH v2] arm64: hw_breakpoint: use target state to determine ABI behaviour Date: Wed, 7 Oct 2015 11:37:36 +0100 Message-Id: <1444214256-24158-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151007_033800_833828_EB68D273 X-CRM114-Status: GOOD ( 15.38 ) X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.96.50 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: Catalin Marinas , Yao Qi , Will Deacon , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: will.deacon@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The arm64 hw_breakpoint interface is slightly less flexible than its 32-bit counterpart, thanks to some changes in the architecture rendering unaligned watchpoint addresses obselete for AArch64. However, in a multi-arch environment (i.e. debugging a 32-bit target with a 64-bit GDB under a 64-bit kernel), we need to provide a feature compatible interface to GDB in order for debugging to function correctly. This patch adds a new helper, is_compat_bp, to our hw_breakpoint implementation which changes the interface behaviour based on the architecture of the debug target as opposed to the debugger itself. This allows debugged to function as expected for multi-arch configurations without relying on deprecated architectural behaviours when debugging native applications. Cc: Yao Qi Cc: Catalin Marinas Signed-off-by: Will Deacon --- v1 -> v2: Added comment regarding NULL tsk in is_compat_bp arch/arm64/kernel/hw_breakpoint.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c index bba85c8f8037..46465d9fbc4d 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -163,6 +163,20 @@ enum hw_breakpoint_ops { HW_BREAKPOINT_RESTORE }; +static int is_compat_bp(struct perf_event *bp) +{ + struct task_struct *tsk = bp->hw.target; + + /* + * tsk can be NULL for per-cpu (non-ptrace) breakpoints. + * In this case, use the native interface, since we don't have + * the notion of a "compat CPU" and could end up relying on + * deprecated behaviour if we use unaligned watchpoints in + * AArch64 state. + */ + return tsk && is_compat_thread(task_thread_info(tsk)); +} + /** * hw_breakpoint_slot_setup - Find and setup a perf slot according to * operations @@ -420,7 +434,7 @@ static int arch_build_bp_info(struct perf_event *bp) * Watchpoints can be of length 1, 2, 4 or 8 bytes. */ if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { - if (is_compat_task()) { + if (is_compat_bp(bp)) { if (info->ctrl.len != ARM_BREAKPOINT_LEN_2 && info->ctrl.len != ARM_BREAKPOINT_LEN_4) return -EINVAL; @@ -477,7 +491,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) * AArch32 tasks expect some simple alignment fixups, so emulate * that here. */ - if (is_compat_task()) { + if (is_compat_bp(bp)) { if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) alignment_mask = 0x7; else