From patchwork Thu Sep 24 22:31:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 54139 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f71.google.com (mail-la0-f71.google.com [209.85.215.71]) by patches.linaro.org (Postfix) with ESMTPS id 6364322B1E for ; Thu, 24 Sep 2015 22:35:15 +0000 (UTC) Received: by lamf6 with SMTP id f6sf47380163lam.1 for ; Thu, 24 Sep 2015 15:35:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:subject:date:message-id :in-reply-to:references:precedence:list-id:list-unsubscribe :list-archive:list-post:list-help:list-subscribe:cc:mime-version :content-type:content-transfer-encoding:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list; bh=w2m8oCSBtVN8Chj91MpPK4fVbaEgCreU2WYaeSzq1Ck=; b=dbgnmafCRILDIBFoxZdG3eM9fPrXgIyKmeqGr0fXmgK4rbltz5ANqbn6xE/Hs524un ts3CbLWKx1SCX7KMJgxcz3YWOxx+My7q6cP6ERP2u9Bam294neGerEhXI/pnpasKlDVS mHOZn53/Xq9jy3hRvnQq84aB5KubIuj5GqFLGMivl8c0LlR+UbO8APDgugllaLuEuHwC ENt6sB6z6+96J41Y4OWDSll78fKrzxiB3pkq2CAguhQBOTp9IZn8EnNn+Zt9cf1lnbpM ehsZmgkvQ4lF9x0c3I+ibJYUIbJFQ14CBn++t3zDxXJto21YUMwEKBKSNfpG7wnodbk3 cHqw== X-Gm-Message-State: ALoCoQkbSIQFKT7aYurchjmdDzntY5SmsMuuOBYGgNzAaJZE96LbYi4Gr5+rjYLiZBZn/EVN+u0z X-Received: by 10.180.107.167 with SMTP id hd7mr442481wib.6.1443134114297; Thu, 24 Sep 2015 15:35:14 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.19.134 with SMTP id f6ls139490lae.74.gmail; Thu, 24 Sep 2015 15:35:14 -0700 (PDT) X-Received: by 10.112.54.169 with SMTP id k9mr592482lbp.95.1443134114153; Thu, 24 Sep 2015 15:35:14 -0700 (PDT) Received: from mail-la0-f47.google.com (mail-la0-f47.google.com. [209.85.215.47]) by mx.google.com with ESMTPS id ir2si252385lac.75.2015.09.24.15.35.14 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Sep 2015 15:35:14 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) client-ip=209.85.215.47; Received: by lacdq2 with SMTP id dq2so24617483lac.1 for ; Thu, 24 Sep 2015 15:35:14 -0700 (PDT) X-Received: by 10.112.64.72 with SMTP id m8mr601222lbs.41.1443134113993; Thu, 24 Sep 2015 15:35:13 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp586024lbq; Thu, 24 Sep 2015 15:35:13 -0700 (PDT) X-Received: by 10.68.88.130 with SMTP id bg2mr2547538pbb.129.1443134112979; Thu, 24 Sep 2015 15:35:12 -0700 (PDT) Received: from bombadil.infradead.org (bombadil.infradead.org. [2001:1868:205::9]) by mx.google.com with ESMTPS id xm2si724160pbb.66.2015.09.24.15.35.12 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Sep 2015 15:35:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF5X-0000QF-CV; Thu, 24 Sep 2015 22:34:03 +0000 Received: from mail-pa0-f43.google.com ([209.85.220.43]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF4K-00078V-0H for linux-arm-kernel@lists.infradead.org; Thu, 24 Sep 2015 22:32:48 +0000 Received: by padhy16 with SMTP id hy16so85167174pad.1 for ; Thu, 24 Sep 2015 15:32:27 -0700 (PDT) X-Received: by 10.66.124.229 with SMTP id ml5mr631150pab.77.1443133947318; Thu, 24 Sep 2015 15:32:27 -0700 (PDT) Received: from localhost.localdomain ([40.139.248.3]) by smtp.gmail.com with ESMTPSA id ll9sm325723pbc.42.2015.09.24.15.32.22 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 15:32:26 -0700 (PDT) From: Shannon Zhao To: kvmarm@lists.cs.columbia.edu Subject: [PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register Date: Thu, 24 Sep 2015 15:31:13 -0700 Message-Id: <1443133885-3366-9-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> References: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150924_153248_082774_548777B7 X-CRM114-Status: GOOD ( 13.35 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.43 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.43 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or reset_unknown_cp15 for its reset handler. Add access handler which emulates writing and reading PMXEVTYPER register. When writing to PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event for the selected event type. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d49657a..605972e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -488,6 +488,13 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case PMXEVTYPER_EL0: { + val = vcpu_sys_reg(vcpu, PMSELR_EL0); + kvm_pmu_set_counter_event_type(vcpu, + *vcpu_reg(vcpu, p->Rt), + val); + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -728,7 +735,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { trap_raz_wi }, /* PMXEVTYPER_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMXEVTYPER_EL0 }, /* PMXEVCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010), trap_raz_wi }, @@ -944,6 +951,13 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case c9_PMXEVTYPER: { + val = vcpu_cp15(vcpu, c9_PMSELR); + kvm_pmu_set_counter_event_type(vcpu, + *vcpu_reg(vcpu, p->Rt), + val); + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -1006,7 +1020,8 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs, reset_pmceid, c9_PMCEID1 }, { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMXEVTYPER }, { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },