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[2001:1868:205::9]) by mx.google.com with ESMTPS id cl4si742553pad.26.2015.09.24.15.37.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Sep 2015 15:37:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF7v-0004nn-3b; Thu, 24 Sep 2015 22:36:31 +0000 Received: from mail-pa0-f53.google.com ([209.85.220.53]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF4m-0007X7-VS for linux-arm-kernel@lists.infradead.org; Thu, 24 Sep 2015 22:33:18 +0000 Received: by pacgz1 with SMTP id gz1so2652918pac.3 for ; Thu, 24 Sep 2015 15:32:56 -0700 (PDT) X-Received: by 10.67.8.106 with SMTP id dj10mr2563048pad.123.1443133976238; Thu, 24 Sep 2015 15:32:56 -0700 (PDT) Received: from localhost.localdomain ([40.139.248.3]) by smtp.gmail.com with ESMTPSA id ll9sm325723pbc.42.2015.09.24.15.32.51 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 15:32:55 -0700 (PDT) From: Shannon Zhao To: kvmarm@lists.cs.columbia.edu Subject: [PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register Date: Thu, 24 Sep 2015 15:31:19 -0700 Message-Id: <1443133885-3366-15-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> References: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150924_153317_100169_A6A291D4 X-CRM114-Status: GOOD ( 12.83 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.53 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.53 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.50 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. While the reset value of PMUSERENR is zero, use reset_val_cp15 with zero for its reset handler. Add a helper for CP15 registers reset to specified value. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 5 +++-- arch/arm64/kvm/sys_regs.h | 8 ++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 6f76dc8..749e1e2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -805,7 +805,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMXEVCNTR_EL0 }, /* PMUSERENR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMUSERENR_EL0 }, /* PMOVSSET_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011), access_pmu_regs, reset_unknown, PMOVSSET_EL0 }, @@ -1156,7 +1156,8 @@ static const struct sys_reg_desc cp15_regs[] = { reset_unknown_cp15, c9_PMXEVTYPER }, { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMXEVCNTR }, - { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmu_cp15_regs, + reset_val_cp15, c9_PMUSERENR, 0 }, { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMINTENSET }, { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs, diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h index 8afeff7..aba997d 100644 --- a/arch/arm64/kvm/sys_regs.h +++ b/arch/arm64/kvm/sys_regs.h @@ -125,6 +125,14 @@ static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r vcpu_sys_reg(vcpu, r->reg) = r->val; } +static inline void reset_val_cp15(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r) +{ + BUG_ON(!r->reg); + BUG_ON(r->reg >= NR_SYS_REGS); + vcpu_cp15(vcpu, r->reg) = r->val; +} + static inline int cmp_sys_reg(const struct sys_reg_desc *i1, const struct sys_reg_desc *i2) {