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[2001:1868:205::9]) by mx.google.com with ESMTPS id fa7si686822pad.180.2015.09.24.15.37.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Sep 2015 15:37:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF7R-0004FP-1j; Thu, 24 Sep 2015 22:36:01 +0000 Received: from mail-pa0-f47.google.com ([209.85.220.47]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF4d-0007OL-5A for linux-arm-kernel@lists.infradead.org; Thu, 24 Sep 2015 22:33:09 +0000 Received: by pacex6 with SMTP id ex6so85034091pac.0 for ; Thu, 24 Sep 2015 15:32:46 -0700 (PDT) X-Received: by 10.66.236.129 with SMTP id uu1mr2657904pac.34.1443133966497; Thu, 24 Sep 2015 15:32:46 -0700 (PDT) Received: from localhost.localdomain ([40.139.248.3]) by smtp.gmail.com with ESMTPSA id ll9sm325723pbc.42.2015.09.24.15.32.41 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 15:32:45 -0700 (PDT) From: Shannon Zhao To: kvmarm@lists.cs.columbia.edu Subject: [PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Date: Thu, 24 Sep 2015 15:31:17 -0700 Message-Id: <1443133885-3366-13-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> References: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150924_153307_663314_DE26B069 X-CRM114-Status: GOOD ( 13.27 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.47 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.220.47 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.48 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMINTENSET or PMINTENCLR register. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 98da5a2..e52325c 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -519,6 +519,18 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; break; } + case PMINTENSET_EL1: { + val = *vcpu_reg(vcpu, p->Rt); + vcpu_sys_reg(vcpu, r->reg) |= val; + vcpu_sys_reg(vcpu, PMINTENCLR_EL1) |= val; + break; + } + case PMINTENCLR_EL1: { + val = *vcpu_reg(vcpu, p->Rt); + vcpu_sys_reg(vcpu, r->reg) &= ~val; + vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -708,10 +720,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* PMINTENSET_EL1 */ { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMINTENSET_EL1 }, /* PMINTENCLR_EL1 */ { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMINTENCLR_EL1 }, /* MAIR_EL1 */ { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000), @@ -1022,6 +1034,18 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val; break; } + case c9_PMINTENSET: { + val = *vcpu_reg(vcpu, p->Rt); + vcpu_cp15(vcpu, r->reg) |= val; + vcpu_cp15(vcpu, c9_PMINTENCLR) |= val; + break; + } + case c9_PMINTENCLR: { + val = *vcpu_reg(vcpu, p->Rt); + vcpu_cp15(vcpu, r->reg) &= ~val; + vcpu_cp15(vcpu, c9_PMINTENSET) &= ~val; + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -1108,8 +1132,10 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMXEVCNTR }, { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMINTENSET }, + { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMINTENCLR }, { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },