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[2001:1868:205::9]) by mx.google.com with ESMTPS id ge9si741356pbc.39.2015.09.24.15.37.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Sep 2015 15:37:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF7E-0003yZ-45; Thu, 24 Sep 2015 22:35:48 +0000 Received: from mail-pa0-f50.google.com ([209.85.220.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF4Y-0007JX-1I for linux-arm-kernel@lists.infradead.org; Thu, 24 Sep 2015 22:33:04 +0000 Received: by pacfv12 with SMTP id fv12so86498600pac.2 for ; Thu, 24 Sep 2015 15:32:41 -0700 (PDT) X-Received: by 10.68.132.234 with SMTP id ox10mr2621660pbb.128.1443133961604; Thu, 24 Sep 2015 15:32:41 -0700 (PDT) Received: from localhost.localdomain ([40.139.248.3]) by smtp.gmail.com with ESMTPSA id ll9sm325723pbc.42.2015.09.24.15.32.37 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 15:32:40 -0700 (PDT) From: Shannon Zhao To: kvmarm@lists.cs.columbia.edu Subject: [PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Date: Thu, 24 Sep 2015 15:31:16 -0700 Message-Id: <1443133885-3366-12-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> References: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150924_153302_300558_1F910102 X-CRM114-Status: GOOD ( 17.99 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.50 listed in wl.mailspike.net] -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.50 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.47 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use reset_unknown for its reset handler. Add a new case to emulate writing PMCNTENSET or PMCNTENCLR register. When writing to PMCNTENSET, call perf_event_enable to enable the perf event. When writing to PMCNTENCLR, call perf_event_disable to disable the perf event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 46 +++++++++++++++++++++++++++++++++++++++++---- include/kvm/arm_pmu.h | 4 ++++ virt/kvm/arm/pmu.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c38c2de..98da5a2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -501,6 +501,24 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, val); break; } + case PMCNTENSET_EL0: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_enable_counter(vcpu, val); + /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means + * corresponding counter enabled */ + vcpu_sys_reg(vcpu, r->reg) |= val; + vcpu_sys_reg(vcpu, PMCNTENCLR_EL0) |= val; + break; + } + case PMCNTENCLR_EL0: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_disable_counter(vcpu, val); + /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means + * corresponding counter disabled */ + vcpu_sys_reg(vcpu, r->reg) &= ~val; + vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; + break; + } case PMCR_EL0: { /* Only update writeable bits of PMCR */ val = vcpu_sys_reg(vcpu, r->reg); @@ -733,10 +751,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_pmcr, PMCR_EL0, }, /* PMCNTENSET_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMCNTENSET_EL0 }, /* PMCNTENCLR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMCNTENCLR_EL0 }, /* PMOVSCLR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011), trap_raz_wi }, @@ -986,6 +1004,24 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, val); break; } + case c9_PMCNTENSET: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_enable_counter(vcpu, val); + /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means + * corresponding counter enabled */ + vcpu_cp15(vcpu, r->reg) |= val; + vcpu_cp15(vcpu, c9_PMCNTENCLR) |= val; + break; + } + case c9_PMCNTENCLR: { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_disable_counter(vcpu, val); + /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means + * corresponding counter disabled */ + vcpu_cp15(vcpu, r->reg) &= ~val; + vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val; + break; + } case c9_PMCR: { /* Only update writeable bits of PMCR */ val = vcpu_cp15(vcpu, r->reg); @@ -1054,8 +1090,10 @@ static const struct sys_reg_desc cp15_regs[] = { /* PMU */ { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs, reset_pmcr, c9_PMCR }, - { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMCNTENSET }, + { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMCNTENCLR }, { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMSELR }, diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index b48cdc6..9b4ee5e 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -39,6 +39,8 @@ struct kvm_pmu { #ifdef CONFIG_KVM_ARM_PMU unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx); +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val); +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val); void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx); #else @@ -46,6 +48,8 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx) { return 0; } +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) {} +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val) {} void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data, u32 select_idx) {} #endif diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index 002ec79..46145d1 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -86,6 +86,54 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx) } /** + * kvm_pmu_enable_counter - enable selected PMU counter + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMCNTENSET register + * + * Call perf_event_enable to start counting the perf event + */ +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val) +{ + int i; + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc; + + for (i = 0; i < 32; i++) { + if ((val >> i) & 0x1) { + pmc = &pmu->pmc[i]; + if (pmc->perf_event) { + perf_event_enable(pmc->perf_event); + if (pmc->perf_event->state + != PERF_EVENT_STATE_ACTIVE) + kvm_debug("fail to enable event\n"); + } + } + } +} + +/** + * kvm_pmu_disable_counter - disable selected PMU counter + * @vcpu: The vcpu pointer + * @val: the value guest writes to PMCNTENCLR register + * + * Call perf_event_disable to stop counting the perf event + */ +void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) +{ + int i; + struct kvm_pmu *pmu = &vcpu->arch.pmu; + struct kvm_pmc *pmc; + + for (i = 0; i < 32; i++) { + if ((val >> i) & 0x1) { + pmc = &pmu->pmc[i]; + if (pmc->perf_event) + perf_event_disable(pmc->perf_event); + } + } +} + +/** * kvm_pmu_set_counter_event_type - set selected counter to monitor some event * @vcpu: The vcpu pointer * @data: The data guest writes to PMXEVTYPER_EL0