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[2001:1868:205::9]) by mx.google.com with ESMTPS id fl1si745164pab.174.2015.09.24.15.47.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Sep 2015 15:47:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfFGz-0007WW-Ae; Thu, 24 Sep 2015 22:45:53 +0000 Received: from mail-pa0-f52.google.com ([209.85.220.52]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZfF4P-0007DI-Kn for linux-arm-kernel@lists.infradead.org; Thu, 24 Sep 2015 22:32:54 +0000 Received: by pacgz1 with SMTP id gz1so2644974pac.3 for ; Thu, 24 Sep 2015 15:32:33 -0700 (PDT) X-Received: by 10.66.186.39 with SMTP id fh7mr2686652pac.48.1443133952253; Thu, 24 Sep 2015 15:32:32 -0700 (PDT) Received: from localhost.localdomain ([40.139.248.3]) by smtp.gmail.com with ESMTPSA id ll9sm325723pbc.42.2015.09.24.15.32.27 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 15:32:31 -0700 (PDT) From: Shannon Zhao To: kvmarm@lists.cs.columbia.edu Subject: [PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register Date: Thu, 24 Sep 2015 15:31:14 -0700 Message-Id: <1443133885-3366-10-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> References: <1443133885-3366-1-git-send-email-shannon.zhao@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150924_153253_770056_298A4C56 X-CRM114-Status: GOOD ( 13.94 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [209.85.220.52 listed in wl.mailspike.net] -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.52 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shannon.zhao@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value to get the count value of the perf event. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 41 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 605972e..e7f6058 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -488,6 +488,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case PMXEVCNTR_EL0: { + val = PMEVCNTR0_EL0 + vcpu_sys_reg(vcpu, PMSELR_EL0); + vcpu_sys_reg(vcpu, val) = + *vcpu_reg(vcpu, p->Rt) & 0xffffffffUL; + break; + } case PMXEVTYPER_EL0: { val = vcpu_sys_reg(vcpu, PMSELR_EL0); kvm_pmu_set_counter_event_type(vcpu, @@ -511,7 +517,17 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, break; } } else { - *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg); + switch (r->reg) { + case PMXEVCNTR_EL0: { + val = kvm_pmu_get_counter_value(vcpu, + vcpu_sys_reg(vcpu, PMSELR_EL0)); + *vcpu_reg(vcpu, p->Rt) = val; + break; + } + default: + *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg); + break; + } } return true; @@ -738,7 +754,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMXEVTYPER_EL0 }, /* PMXEVCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010), - trap_raz_wi }, + access_pmu_regs, reset_unknown, PMXEVCNTR_EL0 }, /* PMUSERENR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000), trap_raz_wi }, @@ -951,6 +967,12 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, if (p->is_write) { switch (r->reg) { + case c9_PMXEVCNTR: { + val = c14_PMEVCNTR0 + vcpu_cp15(vcpu, c9_PMSELR); + vcpu_cp15(vcpu, val) = + *vcpu_reg(vcpu, p->Rt) & 0xffffffffUL; + break; + } case c9_PMXEVTYPER: { val = vcpu_cp15(vcpu, c9_PMSELR); kvm_pmu_set_counter_event_type(vcpu, @@ -974,7 +996,17 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, break; } } else { - *vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg); + switch (r->reg) { + case c9_PMXEVCNTR: { + val = kvm_pmu_get_counter_value(vcpu, + vcpu_cp15(vcpu, c9_PMSELR)); + *vcpu_reg(vcpu, p->Rt) = val; + break; + } + default: + *vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg); + break; + } } return true; @@ -1022,7 +1054,8 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMXEVTYPER }, - { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs, + reset_unknown_cp15, c9_PMXEVCNTR }, { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },