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[209.132.180.67]) by mx.google.com with ESMTP id lj9si17968171pbc.51.2015.09.24.04.39.34; Thu, 24 Sep 2015 04:39:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754519AbbIXLja (ORCPT + 30 others); Thu, 24 Sep 2015 07:39:30 -0400 Received: from bhuna.collabora.co.uk ([93.93.135.160]:37051 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754431AbbIXLj2 (ORCPT ); Thu, 24 Sep 2015 07:39:28 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sjoerd) with ESMTPSA id 8CEC16091F1 Received: by dusk.luon.net (Postfix, from userid 1000) id 16C9128CBC; Thu, 24 Sep 2015 13:39:20 +0200 (CEST) From: Sjoerd Simons To: linux-rockchip@lists.infradead.org, arm@kernel.org Cc: Thierry Reding , Kevin Hilman , linux-arm-kernel@lists.infradead.org, Heiko Stuebner , Javier Martinez Canillas , Kukjin Kim , Krzysztof Kozlowski , Geert Uytterhoeven , linux-kernel@vger.kernel.org, Russell King , Alexandre Belloni , Arnd Bergmann , Lee Jones , Olof Johansson , Ray Jui , Stephen Warren Subject: [PATCH v2 4/5] ARM: multi_v7_defconfig: Enable the Rockchip USB 2.0 phy Date: Thu, 24 Sep 2015 13:39:18 +0200 Message-Id: <1443094759-28531-5-git-send-email-sjoerd.simons@collabora.co.uk> X-Mailer: git-send-email 2.5.3 In-Reply-To: <1443094759-28531-1-git-send-email-sjoerd.simons@collabora.co.uk> References: <1443094759-28531-1-git-send-email-sjoerd.simons@collabora.co.uk> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: sjoerd.simons@collabora.co.uk X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Most Rockchip SoCs have a DesignWare HS OTG USB 2.0 controller, enable the driver for the Rockchip USB 2.0 PHY to make that functional. Signed-off-by: Sjoerd Simons --- Changes in v2: - Only enable the USB 2 phy, not the controller as that came in through another tree - Enable USB 2.0 phy as a module as the controller is a module as well arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 660e72a..2ce0d63 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -662,6 +662,7 @@ CONFIG_PHY_HIX5HD2_SATA=y CONFIG_PWM_STI=m CONFIG_OMAP_USB2=y CONFIG_TI_PIPE3=y +CONFIG_PHY_ROCKCHIP_USB=m CONFIG_PHY_MIPHY28LP=y CONFIG_PHY_MIPHY365X=y CONFIG_PHY_RCAR_GEN2=m