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[209.132.180.67]) by mx.google.com with ESMTP id a5si7531017igx.13.2015.09.18.09.29.13; Fri, 18 Sep 2015 09:29:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755004AbbIRQ3F (ORCPT + 30 others); Fri, 18 Sep 2015 12:29:05 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]:36166 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754747AbbIRQ1X (ORCPT ); Fri, 18 Sep 2015 12:27:23 -0400 Received: by padhk3 with SMTP id hk3so55053222pad.3 for ; Fri, 18 Sep 2015 09:27:22 -0700 (PDT) X-Received: by 10.68.180.131 with SMTP id do3mr8046967pbc.133.1442593642862; Fri, 18 Sep 2015 09:27:22 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by smtp.gmail.com with ESMTPSA id la4sm9847027pbc.76.2015.09.18.09.27.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Sep 2015 09:27:22 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org, a.p.zijlstra@chello.nl, alexander.shishkin@linux.intel.com, acme@kernel.org, mingo@redhat.com, corbet@lwn.net Cc: adrian.hunter@intel.com, zhang.chunyan@linaro.org, mike.leach@arm.com, tor@ti.com, al.grant@arm.com, pawel.moll@arm.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 15/20] coresight: etm-perf: implementing 'setup_aux()' API Date: Fri, 18 Sep 2015 10:26:29 -0600 Message-Id: <1442593594-10665-16-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> References: <1442593594-10665-1-git-send-email-mathieu.poirier@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: mathieu.poirier@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.170 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Before trace can be collected the PMU needs to get a handle on the mmpap'ed memory that was granted. Since the collection of traces can be done by sink buffers of various types, representation of the memory layout is done at the sink level rather than the tracer PMU driver. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index a21171a3e929..3aeb4215bb22 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -227,6 +227,27 @@ out: return ret; } +static void *etm_setup_aux(int cpu, void **pages, + int nr_pages, bool overwrite) +{ + struct coresight_device *csdev; + + if (cpu == -1) + cpu = smp_processor_id(); + + csdev = per_cpu(csdev_sink, cpu); + if (!csdev) + return NULL; + + return sink_ops(csdev)->setup_aux(csdev, cpu, pages, + nr_pages, overwrite); +} + +static void etm_free_aux(void *data) +{ + kfree(data); +} + static int __init etm_perf_init(void) { etm_pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE; @@ -235,6 +256,8 @@ static int __init etm_perf_init(void) etm_pmu.task_ctx_nr = perf_sw_context; etm_pmu.read = etm_event_read; etm_pmu.event_init = etm_event_init; + etm_pmu.setup_aux = etm_setup_aux; + etm_pmu.free_aux = etm_free_aux; return perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1); }