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[209.132.180.67]) by mx.google.com with ESMTP id d24si17630677ioj.18.2015.09.16.07.23.38; Wed, 16 Sep 2015 07:23:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754319AbbIPOXZ (ORCPT + 29 others); Wed, 16 Sep 2015 10:23:25 -0400 Received: from eu-smtp-delivery-143.mimecast.com ([146.101.78.143]:62362 "EHLO eu-smtp-delivery-143.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754141AbbIPOXL (ORCPT ); Wed, 16 Sep 2015 10:23:11 -0400 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-5-eOOx8JFoQKuY0CmvdC2zUw-11; Wed, 16 Sep 2015 15:23:10 +0100 Received: from e106634-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 16 Sep 2015 15:23:05 +0100 From: "Suzuki K. Poulose" To: linux-arm-kernel@lists.infradead.org Cc: Catalin.Marinas@arm.com, Will.Deacon@arm.com, Mark.Rutland@arm.com, edward.nevill@linaro.org, aph@redhat.com, linux-kernel@vger.kernel.org, andre.przywara@arm.com, ard.biesheuvel@linaro.org, dave.martin@arm.com, marc.zyngier@arm.com, Steve Capper Subject: [PATCH 21/22] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs Date: Wed, 16 Sep 2015 15:21:19 +0100 Message-Id: <1442413280-31885-22-git-send-email-suzuki.poulose@arm.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442413280-31885-1-git-send-email-suzuki.poulose@arm.com> References: <1442413280-31885-1-git-send-email-suzuki.poulose@arm.com> X-OriginalArrivalTime: 16 Sep 2015 14:23:05.0818 (UTC) FILETIME=[340DBBA0:01D0F08B] X-MC-Unique: eOOx8JFoQKuY0CmvdC2zUw-11 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linux-kernel-owner@vger.kernel.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Steve Capper It can be useful for JIT software to be aware of MIDR_EL1 and REVIDR_EL1 to ascertain the presence of any core errata that could affect codegen. This patch exposes these registers through sysfs: /sys/devices/system/cpu/cpu$ID/identification/midr /sys/devices/system/cpu/cpu$ID/identification/revidr where $ID is the cpu number. For big.LITTLE systems, one can have a mixture of cores (e.g. Cortex A53 and Cortex A57), thus all CPUs need to be enumerated. If the kernel does not have valid information to populate these entries with, an empty string is returned to userspace. Signed-off-by: Steve Capper --- arch/arm64/include/asm/cpu.h | 1 + arch/arm64/kernel/cpuinfo.c | 48 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index 8e797b2..f3649f9 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -29,6 +29,7 @@ struct cpuinfo_arm64 { u32 reg_cntfrq; u32 reg_dczid; u32 reg_midr; + u32 reg_revidr; u64 reg_id_aa64dfr0; u64 reg_id_aa64dfr1; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 52331ff..93e0488 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -199,6 +199,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_ctr = read_cpuid_cachetype(); info->reg_dczid = read_cpuid(DCZID_EL0); info->reg_midr = read_cpuid_id(); + info->reg_revidr = read_cpuid(REVIDR_EL1); info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); @@ -247,3 +248,50 @@ void __init cpuinfo_store_boot_cpu(void) boot_cpu_data = *info; init_cpu_features(&boot_cpu_data); } + +#define CPUINFO_ATTR_RO(_name) \ + static ssize_t show_##_name (struct device *dev, \ + struct device_attribute *attr, char *buf) \ + { \ + struct cpuinfo_arm64 *info = &per_cpu(cpu_data, dev->id); \ + \ + if (info->reg_midr) \ + return sprintf(buf, "0x%016x\n", info->reg_##_name); \ + else \ + return 0; \ + } \ + static DEVICE_ATTR(_name, 0444, show_##_name, NULL) + +CPUINFO_ATTR_RO(midr); +CPUINFO_ATTR_RO(revidr); + +static struct attribute *cpuregs_attrs[] = { + &dev_attr_midr.attr, + &dev_attr_revidr.attr, + NULL +}; + +static struct attribute_group cpuregs_attr_group = { + .attrs = cpuregs_attrs, + .name = "identification" +}; + +static int __init cpuinfo_regs_init(void) +{ + int cpu, ret; + + for_each_present_cpu(cpu) { + struct device *dev = get_cpu_device(cpu); + + if (!dev) + return -1; + + ret = sysfs_create_group(&dev->kobj, &cpuregs_attr_group); + if (ret) + return ret; + } + + return 0; +} + +device_initcall(cpuinfo_regs_init);