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[2001:1868:205::9]) by mx.google.com with ESMTPS id cw3si904777pbc.246.2015.09.11.01.58.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 11 Sep 2015 01:58:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZaK9T-0001VK-T5; Fri, 11 Sep 2015 08:57:47 +0000 Received: from merlin.infradead.org ([205.233.59.134]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZaK8y-00013O-9S for linux-arm-kernel@bombadil.infradead.org; Fri, 11 Sep 2015 08:57:16 +0000 Received: from szxga01-in.huawei.com ([58.251.152.64]) by merlin.infradead.org with esmtps (Exim 4.85 #2 (Red Hat Linux)) id 1ZaK8t-0001YN-DD for linux-arm-kernel@lists.infradead.org; Fri, 11 Sep 2015 08:57:14 +0000 Received: from 172.24.1.49 (EHLO SZXEML423-HUB.china.huawei.com) ([172.24.1.49]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CUU27158; Fri, 11 Sep 2015 16:55:54 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML423-HUB.china.huawei.com (10.82.67.154) with Microsoft SMTP Server id 14.3.235.1; Fri, 11 Sep 2015 16:55:44 +0800 From: Shannon Zhao To: Subject: [PATCH v2 07/22] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Date: Fri, 11 Sep 2015 16:55:00 +0800 Message-ID: <1441961715-11688-8-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com> References: <1441961715-11688-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150911_045712_738535_26CA8393 X-CRM114-Status: GOOD ( 11.38 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [58.251.152.64 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [58.251.152.64 listed in wl.mailspike.net] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: wei@redhat.com, kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, peter.huangpeng@huawei.com, linux-arm-kernel@lists.infradead.org, zhaoshenglong@huawei.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, shannon.zhao@linaro.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.54 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Shannon Zhao Add reset handler which gets host value of PMCEID0 or PMCEID1. Since write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. Signed-off-by: Shannon Zhao --- arch/arm64/kvm/sys_regs.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 24b8972..b3bc717 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -251,6 +251,26 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) | (ARMV8_PMCR_MASK & 0xdecafbad); } +static void reset_pmceid(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) +{ + u32 pmceid; + + if (r->reg == PMCEID0_EL0 || r->reg == c9_PMCEID0) { + asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid)); + if (!vcpu_mode_is_32bit(vcpu)) + vcpu_sys_reg(vcpu, r->reg) = pmceid; + else + vcpu_cp15(vcpu, r->reg) = pmceid; + } else { + /* PMCEID1_EL0 or c9_PMCEID1 */ + asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid)); + if (!vcpu_mode_is_32bit(vcpu)) + vcpu_sys_reg(vcpu, r->reg) = pmceid; + else + vcpu_cp15(vcpu, r->reg) = pmceid; + } +} + /* PMU registers accessor. */ static bool access_pmu_regs(struct kvm_vcpu *vcpu, const struct sys_reg_params *p, @@ -268,6 +288,9 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu, vcpu_sys_reg(vcpu, r->reg) = val; break; } + case PMCEID0_EL0: + case PMCEID1_EL0: + return ignore_write(vcpu, p); default: vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt); break; @@ -488,10 +511,10 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmu_regs, reset_unknown, PMSELR_EL0 }, /* PMCEID0_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110), - trap_raz_wi }, + access_pmu_regs, reset_pmceid, PMCEID0_EL0 }, /* PMCEID1_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111), - trap_raz_wi }, + access_pmu_regs, reset_pmceid, PMCEID1_EL0 }, /* PMCCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000), trap_raz_wi }, @@ -692,6 +715,9 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu, vcpu_cp15(vcpu, r->reg) = val; break; } + case c9_PMCEID0: + case c9_PMCEID1: + return ignore_write(vcpu, p); default: vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt); break; @@ -738,8 +764,10 @@ static const struct sys_reg_desc cp15_regs[] = { { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs, reset_unknown_cp15, c9_PMSELR }, - { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi }, - { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi }, + { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs, + reset_pmceid, c9_PMCEID0 }, + { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs, + reset_pmceid, c9_PMCEID1 }, { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi }, { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },